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| preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer features n eight independent t1/e1 transmit and receive framers. n internal ds1 transmit clock synthesisno external oscillator necessary. n comprehensive alarm reporting and performance monitoring: programmable automatic and on-demand alarm transmission. n automatic facility data link: automatic transmission of esf performance report message. n common 2.048 mbits/s, 4.096 mbits/s, or 8.192 mbits/s tdm highway. n dual- or single-rail line-side i/o. n supports one second polling interval for perfor- mance monitoring. n ieee * std. 1149.1 jtag boundary scan. n 3.3 v low-power cmos with 5 v tolerant inputs. n available in 352-pin pbga. t1/e1 framer features n supports t1 framing modes esf, d4, slc ? -96, t1dm dds. n supports g.704 basic and crc-4 multiframe for- mat e1 framing and procedures consistent with g.706. n supports unframed transmission format. n t1 signaling modes: transparent; esf 2-state, 4-state, and 16-state; d4 2-state and 4-state; slc -96 2-state, 4-state, 9-state, and 16-state. e1 signaling modes: transparent and cas. n alarm reporting and performance monitoring per at & t, ansi ? , and itu-t standards. n programmable, independent transmit and receive system interfaces at a 2.048 mhz, 4.096 mhz, or 8.192 mhz data rate. facility data link features n hdlc or transparent mode. n automatic transmission of the esf performance report messages (prm). n detection of the esf prm. n detection of the ansi esf fdl bit-oriented codes. n 64-byte fifo in both transmit and receive direc- tions. n programmable fifo full and empty level interrupt. n user-programmable microprocessor interface. microprocessor interface n 33 mhz read and write access. n 12-bit address, 8-bit data interface. n intel ? or motorola style control interfaces. n directly addressable internal registers. n programmable interrupts. applications n ds3 and e3 port cards for narrowband dxcs. n multiservice switches. n high density ds1 and e1 port cards. n frame relay access devices. n byte-synchronous sdh/sonet mapping. n sonet and sdh drop alignment. n ip and packet routers. * ieee is a registered trademark of the institute of electrical and electronics engineers, inc. ? ansi is a registered trademark of american national standards institute, inc. ? intel is a registered trademark of intel corporation. motorola is a registered trademark of motorola, inc.
table of contents contents page preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 2 lucent technologies inc. features ....................................................................................................................... ............................................ 1 t1/e1 framer features .......................................................................................................... ............................... 1 facility data link features .................................................................................................... ................................... 1 microprocessor interface ....................................................................................................... ................................... 1 applications ................................................................................................................... ........................................... 1 feature descriptions ........................................................................................................... ................................... 10 t1/e1 framer feature descriptions .............................................................................................. ...................... 10 functional description ......................................................................................................... ................................... 11 pin information ................................................................................................................ ....................................... 15 liu-framer interface ........................................................................................................... ................................... 29 liu-framer physical interface.................................................................................................. ........................... 29 line encoding.................................................................................................................. .................................... 31 ds1: zero code suppression (zcs)............................................................................................... .................... 31 cept: high-density bipolar of order 3 (hdb3)................................................................................... ............... 33 frame formats .................................................................................................................. ..................................... 34 t1 framing structures.......................................................................................................... ............................... 34 t1 loss of frame alignment (lfa) ............................................................................................... ...................... 41 t1 frame recovery alignment algorithms......................................................................................... ................. 42 t1 robbed-bit signaling ........................................................................................................ ............................. 43 cept 2.048 basic frame, crc-4 time slot 0, and signaling time slot 16 multiframe structures ................... 45 cept 2.048 basic frame structure ............................................................................................... ..................... 46 cept loss of basic frame alignment (lfa) ....................................................................................... ............... 48 cept loss of frame alignment recovery algorithm ................................................................................ ......... 48 cept time slot 0 crc-4 multiframe structure .................................................................................... .............. 49 cept loss of crc-4 multiframe alignment (lts0mfa).............................................................................. ...... 50 cept loss of crc-4 multiframe alignment recovery algorithms .................................................................... .51 cept time slot 16 multiframe structure ......................................................................................... ................... 55 cept loss of time slot 16 multiframe alignment (lts16mfa)...................................................................... ... 56 cept loss of time slot 16 multiframe alignment recovery algorithm.............................................................. 56 cept time slot 0 fas/not fas control bits...................................................................................... ................. 56 fas/not fas si- and e-bit source ............................................................................................... .................... 56 not fas a-bit (cept remote frame alarm) sources ................................................................................ ..... 57 not fas sa-bit sources......................................................................................................... ........................... 57 sa facility data link access ................................................................................................... ............................ 58 not fas sa stack source and destination ........................................................................................ ............... 59 cept time slot 16 x0x2 control bits........................................................................................... .................. 61 signaling access ............................................................................................................... ..................................... 61 transparent signaling .......................................................................................................... ............................... 61 ds1: robbed-bit signaling...................................................................................................... ............................ 61 cept: time slot 16 signaling................................................................................................... .......................... 62 auxiliary framer i/o timing ................................................................................................... ................................ 63 alarms and performance monitoring .............................................................................................. ........................ 67 interrupt generation ........................................................................................................... ................................. 67 alarm definition ............................................................................................................... .................................... 67 event counters definition ..................................................................................................... .............................. 73 loopback and transmission modes................................................................................................ .................... 75 line test patterns ............................................................................................................. .................................. 78 receive line pattern monitorusing register frm_sr7 ............................................................................ ..... 80 automatic and on-demand commands ............................................................................................... .............. 82 facility data link ............................................................................................................. ....................................... 84 lucent technologies inc. 3 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer table of contents (continued) contents page receive facility data link interface........................................................................................... ..........................84 transmit facility data link interface.......................................................................................... ..........................90 hdlc operation ................................................................................................................. .................................91 transparent mode............................................................................................................... .................................93 diagnostic modes ............................................................................................................... .................................95 phase-lock loop circuit ........................................................................................................ .................................96 framer-system interface ........................................................................................................ ................................98 ds1 modes ...................................................................................................................... ....................................98 cept modes..................................................................................................................... ...................................98 receive elastic store.......................................................................................................... .................................98 transmit elastic store......................................................................................................... .................................98 concentration highway interface ................................................................................................ ............................98 chi parameters ................................................................................................................. ..................................99 chi frame timing............................................................................................................... ...............................101 chi offset programming......................................................................................................... ...........................104 jtag boundary-scan specification ............................................................................................... ...................... 105 principle of the boundary scan................................................................................................. .........................105 test access port controller .................................................................................................... ...........................107 instruction register ........................................................................................................... .................................109 boundary-scan register......................................................................................................... ...........................110 bypass register ................................................................................................................ ..............................110 dcode register................................................................................................................. ...............................110 3-state procedures ............................................................................................................. ...............................110 microprocessor interface....................................................................................................... ................................111 overview ....................................................................................................................... .....................................111 microprocessor configuration modes ............................................................................................. ...................111 microprocessor interface pinout definitions .................................................................................... ..................112 microprocessor clock (mpclk) specifications .................................................................................... .............112 microprocessor interface register address map .................................................................................. .............113 i/o timing ..................................................................................................................... .....................................113 reset.......................................................................................................................... .......................................... 118 hardware reset (pin c19)....................................................................................................... ..........................118 software reset/software restart................................................................................................ .......................118 interrupt generation ........................................................................................................... ...................................118 register architecture.......................................................................................................... ...................................119 global register architecture ................................................................................................... ..............................123 global register structure...................................................................................................... ................................123 framer block interrupt status register (greg0)................................................................................. .............123 framer block interrupt enable register (greg1)................................................................................. ............124 fdl block interrupt status enable register (greg2) ............................................................................. .........124 fdl block interrupt enable register (greg3) .................................................................................... .............124 global control register (greg4)................................................................................................ ......................125 device id and version registers (greg5greg7) .................................................................................. .....125 global control register (greg8)................................................................................................ ......................126 global pllck control register (greg9) .......................................................................................... ...............127 framer register architecture ................................................................................................... .............................127 framer status/counter registers ................................................................................................ ......................128 framer parameter/control registers ............................................................................................. ....................141 fdl register architecture...................................................................................................... ...............................168 fdl parameter/control registers ((a00a0e); (a20a2e); (b00b0e); (b20b2e) (c00c0e); (c20c2e); (d00d0e); (d20d2e)) .................................................................169 contents page preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 4 lucent technologies inc. table of contents (continued) register maps .................................................................................................................. .................................... 176 global registers............................................................................................................... ................................. 176 framer parameter/control registers (read-write)................................................................................ ........... 177 receive framer signaling registers (read-only) ................................................................................. ........... 179 framer unit parameter register map ............................................................................................. .................. 180 transmit signaling registers (read/write) ...................................................................................... ................. 183 facility data link parameter/control and status registers (read-write)......................................................... 184 absolute maximum ratings....................................................................................................... ........................... 185 operating conditions........................................................................................................... ................................. 185 handling precautions ........................................................................................................... ................................ 185 electrical characteristics ..................................................................................................... ................................. 186 logic interface characteristics ................................................................................................ .......................... 186 power supply bypassing......................................................................................................... ............................. 186 outline diagram................................................................................................................ .................................... 187 352-pin pbga ................................................................................................................... ................................ 187 ordering information........................................................................................................... .................................. 188 figures page figure 1. TFRA08C13 block diagram (one of eight channels)...................................................................... ....... 11 figure 2. TFRA08C13 block diagram: receive section (one of eight channels)................................................. 13 figure 3. TFRA08C13 block diagram: transmit section (one of eight channels) ................................................ 14 figure 4. pin assignment ....................................................................................................... ................................ 15 figure 5. block diagram of framer line interface ............................................................................... ................... 29 figure 6. transmit framer tlck to tnd, tpd and receive framer rnd, rpd to rlck timing ......................... 30 figure 7. t1 frame structure ................................................................................................... .............................. 34 figure 8. t1 transparent frame structure ....................................................................................... ...................... 35 figure 9. t7633 facility data link access timing of the transmit and receive framer sections ......................... 37 figure 10. slc- 96 frame format................................................................................................................ ........... 37 figure 11. itu 2.048 basic frame, crc-4 multiframe, and channel associated signaling multiframe structures ................................................................................................ .......................... 45 figure 12. cept transparent frame structure .................................................................................... .................. 47 figure 13. receive crc-4 multiframe search algorithm using the 100 ms internal timer................................... 52 figure 14. receive crc-4 multiframe search algorithm for automatic, crc-4/non-crc-4 equipment interworking as defined by itu (from itu rec. g.706, annex b.2.2 - 1991)..................................................... 54 figure 15. facility data link access timing of the transmit and receive framer sections in the cept mode............................................................................................... ..................... 58 figure 16. transmit and receive sa stack accessing protocol .................................................................... ......... 60 figure 17. timing specification for rfrmck, rfrmdata, and rfs in ds1 mode .............................................. 63 figure 18. timing specification for tfs, tlck, and tpd in ds1 mode ............................................................. ... 63 figure 19. timing specification for rfrmck, rfrmdata, and rfs in cept mode ........................................... 64 figure 20. timing specification for rfrmck, rfrmdata, rfs, and rssfs in cept mode ............................. 64 figure 21. timing specification for rcrcmfs in cept mode....................................................................... ....... 65 figure 22. timing specification for tfs, tlck, and tpd in cept mode............................................................ .. 65 figure 23. timing specification for tfs, tlck, tpd, and tssfs in cept mode ................................................ 66 figure 24. timing specification for tfs, tlck, tpd, and tcrcmfs in cept mode .......................................... 66 figure 25. relation between rlck1 and interrupt (pin ad8)...................................................................... .......... 67 figure 26. timing for generation of lopllck (pin f25).......................................................................... ............. 69 figure 27. the t and v reference points for a typical cept e1 application...................................................... .. 72 figure 28. loopback and test transmission modes................................................................................ ............... 77 lucent technologies inc. 5 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer table of contents (continued) figures page figure 29. 20-stage shift register used to generate the quasi-random signal ..................................................78 figure 30. 15-stage shift register used to generate the pseudorandom signal ..................................................79 figure 31. TFRA08C13 facility data link access timing of the transmit and receive framer sections ..............84 figure 32. block diagram for the receive facility data link interface.......................................................... ..........85 figure 33. block diagram for the transmit facility data link interface ......................................................... ..........90 figure 34. local loopback mode ................................................................................................. ...........................95 figure 35. remote loopback mode ................................................................................................ ........................96 figure 36. TFRA08C13 phase detector circuitry .................................................................................. .................97 figure 37. nominal concentration highway interface timing (for frm_pr43 bit 0bit 2 = 100 (binary)) ..........101 figure 38. chidts mode concentration highway interface timing .................................................................. ...102 figure 39. associated signaling mode concentration highway interface timing .................................................103 figure 40. chi timing with asm and chidts enabled .............................................................................. .........103 figure 41. tchidata and rchidata to chick relationship with cms = 0 (cex = 3 and cer = 4, respectively) ............................................................................................ ...................104 figure 42. receive chi (rchidata) timing....................................................................................... ..................105 figure 43. transmit chi (tchidata) timing ...................................................................................... ..................105 figure 44. block diagram of the TFRA08C13's boundary-scan test logic .........................................................10 6 figure 45. bs tap controller state diagram ..................................................................................... ...................107 figure 46. mode 1read cycle timing (mpmode = 0) ............................................................................... ......116 figure 47. mode 1write cycle timing (mpmode = 0).............................................................................. ........116 figure 48. mode 3read cycle timing (mpmode = 1) ............................................................................... ......117 figure 49. mode 3write cycle timing (mpmode = 1).............................................................................. ........117 tables page table 1. pin assignments for 352-pin pbga by pin number order................................................................. ......16 table 2. pin descriptions..................................................................................................... ...................................18 table 3. ami encoding ......................................................................................................... ..................................31 table 4. ds1 zcs encoding..................................................................................................... ..............................32 table 5. ds1 b8zs encoding.................................................................................................... .............................32 table 6. ituhdb3 coding ....................................................................................................... ...............................33 table 7. t-carrier hierarchy.................................................................................................. ..................................34 table 8. d4 superframe format ................................................................................................. ............................36 table 9. dds channel-24 format ................................................................................................ ..........................37 table 10. slc -96 data link block format ..................................................................................................... ........38 table 11. slc -96 line switch message codes .................................................................................................. ...39 table 12. transmit and receive slc -96 stack structure.......................................................................................39 table 13. extended superframe (esf) structure................................................................................. ..................40 table 14. t1 loss of frame alignment criteria ................................................................................. .....................41 table 15. t1 frame alignment procedures ....................................................................................... .....................42 table 16. robbed-bit signaling options........................................................................................ .........................43 table 17. slc -96 9-state signaling format ................................................................................................... ........43 table 18.16-state signaling format ............................................................................................ ...........................44 table 19. allocation of bits 1 to 8 of the fas frame and the not fas frame .................................................... ..46 table 20. itu crc-4 multiframe structure...................................................................................... .......................49 table 21. itu cept time slot 16 channel associated signaling multiframe structure ........................................55 table 22. transmit and receive sa stack structure............................................................................. ..................59 table 23. associated signaling mode chi 2-byte time-slot format for ds1 frames ...........................................62 table 24. associated signaling mode chi 2-byte time-slot format for stuffed channels....................................62 table of contents (continued) tables page preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 6 lucent technologies inc. table 25. associated signaling mode chi 2-byte time-slot format for cept..................................................... 6 2 table 26. red alarm or loss of frame alignment conditions ..................................................................... .......... 68 table 27. remote frame alarm conditions ....................................................................................... .................... 68 table 28. alarm indication signal conditions .................................................................................. ...................... 69 table 29. sa6 bit coding recognized by the receive framer. .................................................................... ......... 71 table 30. sa6 bit coding of nt1 interface events recognized by the receive framer........................................ 71 table 31. auxp synchronization and clear synchronization process.............................................................. .... 72 table 32. event counters definition ........................................................................................... ........................... 73 table 33. summary of the deactivation of sstsslb and sstsllb modes as a function of activating the primary loopback modes .............................................................................. ............ 76 table 34. register frm_pr69 test patterns ..................................................................................... ................... 79 table 35. register frm_pr70 test patterns ..................................................................................... ................... 80 table 36. automatic enable commands........................................................................................... ..................... 82 table 37. on-demand commands .................................................................................................. ...................... 83 table 38. receive ansi code .......................................................................................................................... ..... 86 table 39. performance report message structure................................................................................ ................ 86 table 40. fdl performance report message field definition..................................................................... .......... 87 table 41. octet contents and definition ....................................................................................... ......................... 87 table 42. receive status of frame byte........................................................................................ ........................ 88 table 43. hdlc frame format................................................................................................... ........................... 91 table 44. receiver operation in transparent mode.............................................................................. ................. 94 table 45. summary of the TFRA08C13s concentration highway interface parameters ...................................... 99 table 46. programming values for toff[2:0] and roff[2:0] when cms = 0 .................................................... 104 table 47. tap controller states in the data register branch................................................................... ........... 108 table 48. tap controller states in the instruction register branch............................................................ ......... 108 table 49. TFRA08C13s boundary-scan instructions .............................................................................. ........... 109 table 50. idcode register..................................................................................................... ............................ 110 table 51. microprocessor configuration modes .................................................................................. ................ 111 table 52. mode [1 and 3] microprocessor pin definitions....................................................................... ............. 112 table 53. microprocessor input clock specifications ........................................................................... ............... 112 table 54. TFRA08C13 register address map...................................................................................... ............... 113 table 55. microprocessor interface i/o timing specifications .................................................................. ........... 114 table 56. status register and corresponding interrupt enable register for functional blocks.......................... 118 table 57. asserted value and deasserted state for greg4 bit 4 and bit 6 logic combinations ...................... 118 table 58. register summary .................................................................................................... ........................... 119 table 59. global register set (0x0000x009) ................................................................................... ................ 123 table 60. framer block interrupt status register (greg0) (000)................................................................ ....... 123 table 61. framer block interrupt enable register (greg1) (001)................................................................ ...... 124 table 62. fdl block interrupt status register (greg2) (002) ................................................................... ........ 124 table 63. fdl block interrupt enable register (greg3) (003) ................................................................... ....... 124 table 64. global control register (greg4) (004) ............................................................................... ............... 125 table 65. device id and version registers (greg5greg7) (005007) ...................................................... 125 table 66. global control register (greg8) (008) ............................................................................... ............... 126 table 67. global pllck control register (greg9) (009) ......................................................................... ......... 127 table 68. framer status and control blocks address range (hexadecimal)...................................................... 12 7 table 69. interrupt status register (frm_sr0) (y00) ........................................................................... ............. 128 table 70. facility alarm condition register (frm_sr1) (y01) ................................................................... ........ 129 table 71. remote end alarm register (frm_sr2) (y02) ........................................................................... ....... 130 table 72. facility errored event register-1 (frm_sr3) (y03) ................................................................... ........ 131 lucent technologies inc. 7 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer table of contents (continued) tables pag e table 73. facility event register-2 (frm_sr4) (y04) .......................................................................... ..............132 table 74. exchange termination and exchange termination remote end interface status register (frm_sr5) (y05) .................................................................................. ............133 table 75. network termination and network termination remote end interface status register (frm_sr6) (y06)...................................................................................... ................134 table 76. facility event register (frm_sr7) (y07) ............................................................................. ...............135 table 77. bipolar violation counter registers (frm_sr8frm_sr9) (y08y09) .........................................135 table 78. framing bit error counter registers (frm_sr10frm_sr11) (y0ay0b)....................................135 table 79. crc error counter registers (frm_sr12frm_sr13) (y0cy0d) .............................................136 table 80. e-bit counter registers (frm_sr14frm_sr15) (y0ey0f) .......................................................136 table 81. crc-4 errors at nt1 from nt2 counter registers (frm_sr16frm_sr17) (y10y11) ..............136 table 82. e bit at nt1 from nt2 counter (frm_sr18frm_sr19) (y12y13) ............................................136 table 83. et errored seconds counter (frm_sr20frm_sr21) (y14y15) ...............................................137 table 84. et bursty errored seconds counter (frm_sr22frm_sr23) (y16y17) ....................................137 table 85. et severely errored seconds counter (frm_sr24frm_sr25) (y18y19) ................................137 table 86. et unavailable seconds counter (frm_sr26frm_sr27) (y1ay1b)........................................137 table 87. et-re errored seconds counter (frm_sr28frm_sr29) (y1cy1d) ........................................137 table 88. et-re bursty errored seconds counter (frm_sr30frm_sr31) (y1ey1f)..............................137 table 89. et-re severely errored seconds counter (frm_sr32frm_sr33) (y20y21)...........................137 table 90. et-re unavailable seconds counter (frm_sr34frm_sr35) (y22y23) ...................................138 table 91. nt1 errored seconds counter (frm_sr36frm_sr37) (y24y25).............................................138 table 92. nt1 bursty errored seconds counter (frm_sr38frm_sr39) (y26y27)..................................138 table 93. nt1 severely errored seconds counter (frm_sr40frm_sr41) (y28y29) ..............................138 table 94. nt1 unavailable seconds counter (frm_sr42frm_sr43) (y2ay2b)......................................138 table 95. nt1-re errored seconds counter (frm_sr44frm_sr45) (y2cy2d) .....................................138 table 96. nt1-re bursty errored seconds counter (frm_sr46frm_sr47) (y2ey2f) ...........................138 table 97. nt1-re severely errored seconds counter (frm_sr48frm_sr49) (y30y31) ........................138 table 98. nt1-re unavailable seconds counter (frm_sr50frm_sr51) (y32y33) ................................139 table 99. receive not-fas ts0 register (frm_sr52) (y34) ....................................................................... ....139 table 100. receive sa register (frm_sr53) (y35) ............................................................................... ............139 table 101. slc -96 fdl receive stack (frm_sr54frm_sr63) (y36y3f) ...............................................139 table 102. cept sa receive stack (frm_sr54frm_sr63) (y36y3f) ....................................................140 table 103. transmit framer ansi performance report message status register structure ..............................140 table 104. received signaling registers: ds1 format (frm_rsr0frm_rsr23) (y40y58) ....................140 table 105. receive signaling registers: cept format (frm_rsr0frm_rsr31) (y40y5f) ...................141 table 106. summary of interrupt group enable registers (frm_pr0frm_pr7) (y60y67) ......................141 table 107. primary interrupt group enable register (frm_pr0) (y60) ............................................................ .142 table 108. interrupt enable register (frm_pr1) (y61) .......................................................................... ............142 table 109. interrupt enable register (frm_pr2) (y62) .......................................................................... ............142 table 110. interrupt enable register (frm_pr3) (y63) .......................................................................... ............142 table 111. interrupt enable register (frm_pr4) (y64) .......................................................................... ............143 table 112. interrupt enable register (frm_pr5) (y65) .......................................................................... ............143 table 113. interrupt enable register (frm_pr6) (y66) .......................................................................... ............143 table 114. interrupt enable register (frm_pr7) (y67) .......................................................................... ............143 table 115. framer mode bits decoding (frm_pr8) (y68) .......................................................................... .......143 table 116. line code option bits decoding (frm_pr8) (y68)..................................................................... ......144 table 117. crc option bits decoding (frm_pr9) (y69) ........................................................................... ........144 table 118. alarm filter register (frm_pr10) (y6a)............................................................................. ..............145 table 119. errored event threshold definition................................................................................. ....................145 table 120. errored second threshold register (frm_pr11) (y6b) ................................................................. ..146 table of contents (continued) tables page preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 8 lucent technologies inc. table 121. severely errored second threshold registers (frm_pr12frm_pr13) (y6cy6d) ................ 146 table 122. et1 errored event enable register (frm_pr14) (y6e)................................................................. .. 146 table 123. et1 remote end errored event enable register (frm_pr15) (y6f).............................................. 146 table 124. nt1 errored event enable register (frm_pr16) (y70)................................................................. .. 147 table 125. nt1 remote end errored event enable registers (frm_pr17frm_pr18) (y71y72)............ 147 table 126. automatic ais to the system and automatic loopback enable register (frm_pr19) (y73)........... 147 table 127. automatic ais to the system and automatic loopback enable register (frm_pr19) (y73)........... 148 table 128. transmit test pattern to the line enable register (frm_pr20) (y74) ............................................. 148 table 129. framer fdl control command register (frm_pr21) (y75) ........................................................... 149 table 130. framer transmit line idle code register (frm_pr22) (y76)........................................................... 149 table 131. framer system stuffed time-slot code register (frm_pr23) (y77) .............................................. 149 table 132. primary time-slot loopback address register (frm_pr24) (y78) ................................................. 150 table 133. loopback decoding of bits lbc[2:0] in frm_pr24, bits 75 ......................................................... 15 0 table 134. secondary time-slot loopback address register (frm_pr25) (y79) ............................................ 151 table 135. loopback decoding of bits lbc[1:0] in frm_pr25, bits 65 ......................................................... 15 1 table 136. framer reset and transparent mode control register (frm_pr26) (y7a) ..................................... 152 table 137. transmission of remote frame alarm and cept automatic transmission of a bit = 1 control register (frm_pr27) (y7b) .................................................................... ... 153 table 138. cept automatic transmission of e bit = 0 control register (frm_pr28) (y7c)............................. 154 table 139. sa4sa8 source register (frm_pr29) (y7d) ........................................................................... .... 154 table 140. sa bits source control for bit 5bit 7 in frm_pr29 ................................................................. ...... 155 table 141. sa4sa8 control register (frm_pr30) (y7e) .......................................................................... ..... 155 table 142. sa transmit stack (frm_pr31frm_pr40) (y7fy88).............................................................. 156 table 143. slc -96 transmit stack (frm_pr31frm_pr40) (y7fy88) ...................................................... 156 table 144. transmit slc -96 fdl format ............................................................................................................ 156 table 145. cept time slot 16 x-bit remote multiframe alarm and ais control register (frm_pr41) (y89) .............................................................................................. .................. 157 table 146. framer exercise register (frm_pr42) (y8a) .......................................................................... ........ 157 table 147. framer exercises, frm_pr42 bit 5bit 0 (y8a) ....................................................................... ...... 158 table 148. ds1 system interface control and cept fdl source control register (frm_pr43) (y8b)........... 159 table 149. signaling mode register (frm_pr44) (y8c) ........................................................................... ........ 160 table 150. chi common control register (frm_pr45) (y8d)....................................................................... ... 161 table 151. chi common control register (frm_pr46) (y8e) ....................................................................... ... 162 table 152. chi transmit control register (frm_pr47) (y8f) ..................................................................... ...... 162 table 153. chi receive control register (frm_pr48) (y90) ...................................................................... ...... 162 table 154. chi transmit time-slot enable registers (frm_pr49frm_pr52) (y91y94) ......................... 163 table 155. chi receive time-slot enable registers (frm_pr53frm_pr56) (y95y98) .......................... 163 table 156. chi transmit highway select registers (frm_pr57frm_pr60) (y99y9c)............................ 163 table 157. chi receive highway select registers (frm_pr61frm_pr64) (y9dya0) ............................ 163 table 158. chi transmit control register (frm_pr65) (ya1)..................................................................... ....... 164 table 159. chi receive control register (frm_pr66) (ya2) ...................................................................... ...... 164 table 160. auxiliary pattern generator control register (frm_pr69) (ya5) ..................................................... 1 65 table 161. pattern detector control register (frm_pr70) (ya6) ................................................................. ..... 166 table 162. transmit signaling registers: ds1 format (frm_tsr0frm_tsr23) (ye0yf7) ..................... 167 table 163. transmit signaling registers: cept format (frm_tsr0frm_tsr31) (ye0yff) .................. 167 table 164. fdl register set ((a00a0e); (a20a2e); (b00b0e); (b20b2e) (c00c0e); (c20c2e); (d00d0e); (d20d2e)).................................................................................... .168 table 165. fdl configuration control register (fdl_pr0) (a00; a20; b00; b20; c00; c20; d00; d20) .......... 169 table 166. fdl control register (fdl_pr1) (a01; a21; b01; b21; c01; c21; d01; d21)................................. 169 lucent technologies inc. 9 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer table of contents (continued) tables pag e table 167. fdl interrupt mask control register (fdl_pr2) (a02; a22; b02; b22; c02; c22; d02; d22) .........170 table 168. fdl transmitter configuration control register (fdl_pr3) (a03; a23; b03; b23; c03; c23; d03; d23)....................................................................................... ................171 table 169. fdl transmitter fifo register (fdl_pr4) (a04; a24; b04; b24; c04; c24; d04; d24) ..................171 table 170. fdl transmitter idle character mask register (fdl_pr5) (a05; a25; b05; b25; c05; c25; d05; d25)....................................................................................... ................171 table 171. fdl receiver interrupt level control register (fdl_pr6) (a06; a26; b06; b26; c06; c26; d06; d26)....................................................................................... ................172 table 172. fdl register fdl_pr7............................................................................................... .......................172 table 173. fdl receiver match character register (fdl_pr8) (a08; a28; b08; b28; c08; c28; d08; d28) ...172 table 174. fdl transparent control register (fdl_pr9) (a09; a29; b09; b29; c09; c29; d09; d29)..............173 table 175. fdl transmit ansi esf bit codes (fdl_pr10) (a0a; a2a; b0a; b2a; c0a; c2a; d0a; d2a).......173 table 176. fdl interrupt status register (clear on read) (fdl_sr0) (a0b; a2b; b0b; b2b; c0b; c2b; d0b; d2b) ....................................................................................... ............174 table 177. fdl transmitter status register (fdl_sr1) (a0c; a2c; b0c; b2c; c0c; c2c; d0c; d2c) ...........175 table 178. fdl receiver status register (fdl_sr2) (a0d; a2d; b0d; b2d; c0d; c2d; d0d; d2d) ..............175 table 179. receive ansi fdl status register (fdl_sr3) (a0e; a2e; b0e; b2e; c0e; c2e; d0e; d2e) ........175 table 180. fdl receiver fifo register (fdl_sr4) (a07; a27; b07; b27; c07; c27; d07; d27)......................175 table 181. global register set................................................................................................ .............................176 table 182. framer unit status register map .................................................................................... ...................177 table 183. receive signaling registers map .................................................................................... ...................179 table 184. framer unit parameter register map ................................................................................. ................180 table 185. transmit signaling registers map ................................................................................... ...................183 table 186. facility data link register map .................................................................................... ......................184 table 187. esd threshold voltage.............................................................................................. .........................185 table 188. logic interface characteristics (t a = C40 c to +85 c, v dd = 3.3 v 5%, v ss = 0).........................186 preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 10 lucent technologies inc. lucent technologies inc. feature descriptions t1/e1 framer feature descriptions n framing formats: compliant with t1 standards ansi t1.231 (1993), at&t tr54016, at&t tr62411 (1998). unframed, transparent transmission in t1 and e1 formats. ds1 extended superframe (esf). ds1 superframe (sf): d4; slc -96; t1dm dds; t1dm dds with fdl access. ds1 independent transmit and receive framing modes when using the esf and d4 formats. compliant with itu cept framing recommenda- tion: 1. g.704 and g.706 basic frame format. 2. g.704 section 2.3.3.4 and g.706 section 4.2: crc-4 multiframe search algorithm. 3. g.706 annex b: crc-4 multiframe search algo- rithm with 400 ms timer for interworking of crc-4 and non-crc-4 equipment. 4. g.706 section 4.3.2 note 2: monitoring of 915 crc-4 checksum errors for loss of frame state. n framer line codes: ds1: alternate mark inversion (ami); binary eight zero code suppression (b8zs); per-channel zero code suppression; decoding bipolar violation mon- itor; monitoring of eight or fifteen bit intervals with- out positive or negative pulses error indication. ds1 independent transmit and receive path line code formats when using ami/zcs and b8zs coding. itu-cept: ami; high-density bipolar 3 (hdb3) encoding and decoding bipolar violation monitor- ing, monitoring of four bit intervals without positive or negative pulses error indication. single-rail option. n signaling: ds1: extended superframe 2-state, 4-state, and 16-state per-channel robbed bit. ds1: d4 superframe 2-state and 4-state per- channel robbed bit. ds1: slc -96 superframe 2-state, 4-state, 9-state, and 16-state per-channel robbed bit. ds1: channel-24 message-oriented signaling. itu cept: channel associated signaling (cas). transparent (all data channels). n alarm reporting, performance monitoring, and main- tenance: ansi t1.403-1995, at&t tr 54016, and itu g.826 standard error checking. error and status counters: 1. bipolar violations. 2. errored frame alignment signals. 3. errored crc checksum block. 4. cept: received e bit = 0. 5. errored, severely errored, and unavailable seconds. selectable errored event monitoring for errored and severely errored seconds processing with programmable thresholds for errored and severely errored second monitoring. cept: selectable automatic transmission of e bit to the line. cept: sa6 coded remote end crc-4 error e bit = 0 events. programmable automatic and on-demand alarm transmission: 1. automatic transmission of remote frame alarm to the line while in loss of frame alignment state. 2. automatic transmission of alarm indication signal (ais) to the system while in loss of frame alignment state. multiple loopback modes. optional automatic line and payload loopback acti- vate and deactivate modes. cept nailed-up connect loopback and cept nailed-up broadcast transmission ts-x in ts-0 transmit mode. selectable test patterns for line transmission. detection of framed and unframed pseudorandom and quasi-random test patterns. programmable squelch and idle codes. n system interface: autonomous transmit and receive system inter- faces. independent transmit and receive frame synchro- nization input signals. independent transmit and receive system interface clock. 2.048 mbits/s, 2.048 mhz concentration highway interface (chi) default mode. optional 4.096 mbits/s and 8.192 mbits/s data rates. optional 4.096 mhz and 8.192 mhz frequency system clock. programmable clock edge for latching frame syn- chronization signals. programmable clock edge for latching transmit and receive data. programmable bit and byte offset. programmable chi master mode for the genera- tion of the transmit chi fs from internal logic with timing derived from the receive line clock signal. n digital phase comparator for clock generation in the receive and transmit paths. lucent technologies inc. 11 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. functional description note: the concentration highway interface specification , lucent technologies microelectronics group november 1990 (ds90-124smos) defines the transmit path as output to the system interface, and the receive path as input from the system interface. this document is consistent with that definition. 5-6937(f)r.4 figure 1. TFRA08C13 block diagram (one of eight channels) receive channel [18] microprocessor interface interrupt rdy_dtack wr _ds rd _r/w ale _as cs d[7:0] a[11:0] chick rpd[18] rnd_rbpv[18] rlck[18] cept: ts16) or (ds1: robbed-bit signaling unit receive transmit concentration highway interface phase detector channel digital receive receive facility data link monitor transparent framing) (hdlc or receive framer unit (2 frames) elastic store receive transmit framer unit transmit facility data link monitor transparent framing) (hdlc or xmit framer tclk chick channel [18] transmit receive concentration highway interface (2 frames) elastic store transmit cept: ts16) or (ds1: robbed-bit signaling unit transmit chick chifs tchidata[18] tchidatab[18] rfdl[18], rfdlck[18] rfrmck[18], rfs[18] div-rlck, div-chick, chick-epll rchidata_a[18] tfs[18] div-pllck, div-chick, pllck-epll pllck[18] tfdl[18], tfdlck[18] rchidata_b[18] mpmode (rchi) (tchi) rlck tnd[18], tpd[18], mpck tlck[18] rfrmdata[18], phase detector channel digital transmit encoder decoder synthesizer preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 12 lucent technologies inc. lucent technologies inc. functional description (continued) the lucent technologies microelectronics group TFRA08C13 octal t1/e1 framer provides eight com- plete t1/e1 interfaces each consisting of a fully inte- grated, full-featured, primary rate framer with an hdlc formatter for facility data link access. the TFRA08C13 provides glueless interconnection from a t1 or e1 ana- log line interface to devices interfacing to its chi; for example, the lucent t7270 time-slot interchanger or t7115a synchronous protocol data formatter. the line codes supported in the framer unit include ami, t1 b8zs, per-channel t1 zero code suppression, and itu-cept hdb3. the framer supports ds1 superframe (d4, t1dm, slc -96) and extended superframe (esf) formats. the framer also supports, itu-cept-e1 basic frame, itu-cept-e1 time slot 0 multiframe, and time slot 16 multiframe formats. the receive framer monitors the following alarms: loss of receive clock, loss of frame, alarm indication signal (ais), remote frame alarms, and remote multiframe alarms. these alarms are detected as defined by the appropriate ansi , at&t, and itu standards. it is rec- ommended that the liu/framer interface be placed in dual rail mode, which allows the framers error/event detector to detect and report code and bpv errors. performance monitoring as specified by at&t, ansi , and itu is provided through counters monitoring bipo- lar violation, frame bit errors, crc errors, errored events, errored seconds, bursty errored seconds, severely errored seconds, and unavailable seconds. in-band loopback activation and deactivation codes can be transmitted to the line via the payload or the facility data link. in-band loopback activation and deac- tivation codes in the payload or the facility data link are detected. system, payload, and line loopbacks are programma- ble. the default system interface is a 2.048 mbits/s data and 2.048 mhz clock chi serial bus. this chi interface consists of independent transmit and receive paths. the chi interface can be reconfigured into several modes: a 2.048 mbits/s data interface and 4.096 mhz clock interface, a 4.096 mbits/s data interface and 4.096 mhz clock interface, a 4.096 mbits/s data inter- face and 8.192 mhz clock interface, a 8.192 mbits/s data interface and 8.192 mhz clock interface, and 8.192 mbits/s data interface. the signaling formats supported are t1 per-channel robbed-bit signaling (rbs), channel-24 message-ori- ented signaling (mos), and itu-cept-e1 channel- associated signaling (cas). in the t1, rbs mode voice and data channels are programmable. the entire pay- load can be forced into a data-only (no signaling chan- nels) mode, i.e., transparent mode by programming one control bit. signaling access can be through the on-chip signaling registers or the system chi port in the associated signaling mode. data and its associated signaling information can be accessed through the chi in either ds1 or cept-e1 modes. extraction and insertion of the facility data link in esf, t1dm, slc -96, or cept-e1 modes are provided through a four-port serial interface or through a micro- processor-accessed, 64-byte fifo either with hdlc formatting or transparently. in slc -96 or cept-e1 frame formats, a facility data link (fdl) stack (registers in the framer section) is provided for fdl access. the bit-oriented esf data-link messages defined in ansi t1.403-1995 are monitored by the receive framers facility data link unit. the transmit framers facility data link unit overrides the xfdl-fifo for the transmission of the bit-oriented esf data-link messages defined in ansi t1.403-1995. the receive framer includes a two-frame (64-bytes) elastic store buffer for jitter attenuation that performs controlled slips and provides an indication of slip direc- tion. this buffer can be programmed to operate as a function of the receive line clock and can be reduced to one-frame (32-bytes) in length. lucent technologies inc. 13 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. functional description (continued) accessing internal registers is done via the demultiplexed address and data bus microprocessor interface using either the intel 80188 (or 80x88) interface protocol with independent read and write signals or the motorola mc680x0 or m68360 interface protocol with address and data strobe signals. the TFRA08C13 is manufactured using low-power cmos technology and is packaged in an 352-pin plastic ball grid array (pbga) with 50 mils ball pitch. 5-6965(f) figure 2. TFRA08C13 block diagram: receive section (one of eight channels) transmit concentration highway interface (rate adapter) chifs (2 frames) receive elastic store buffer monitor receive slip internal system clock chick C microprocessor access C concentration highway access C cept channel associated and common channel signaling C ds1 robbed-bit signaling (rbs) receive signaling extracter: rfdlck rfdl & signaling multiframe C cept: basic frame, crc-4 multiframe, C esf C sf: d4, slc -96, dds; realigner, and sync generator: receive t1/e1 frame alignment monitor, C unavailable seconds C severely errored seconds C bursty errored seconds C errored seconds C errored events C bipolar violation errors receive performance monitor: C slips C alarm indication signal (ais) C cept remote multiframe alarm C remote frame alarm C digital loss of signal C analog loss of signal receive alarm monitor: ? message-oriented messages ? bit-oriented messages C ansi t1.403-1989 esf format: C dds access C slc -96 format and monitor: receive facility data link extracter rfrmck rpd, rnd_rbpv rlck receive pattern monitor: C quasi-random: 2 20 C 1 C pseudorandom: 2 15 C 1 C ansi t1.403 bit-oriented and esf-fdl activate and deactivate line loopback codes C cept auxiliary pattern (cept = 01) C cept activate and deactivate loopback C cept sa6 codes C t1/e1 crc errors receive fdl hdlc extracter: C 64-byte receive fifo C transparent mode (no hdlc framing) C microprocessor access tchidata/b codes preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 14 lucent technologies inc. lucent technologies inc. functional description (continued) 5-6964(f) figure 3. TFRA08C13 block diagram: transmit section (one of eight channels) tlck transmit C esf C cept transmit t1/e1 frame formatter, and frame sync generator: C sf: d4, slc -96, dds; signaling C esf C cept: basic frame, crc-4 multiframe, and signaling C transparent framing superframe transmit facility data link C slc -96 format C dds access C ansi t1.403-1989 esf format: ? bit-oriented messages ? message-oriented messages transmit fdl hdlc inserter: C 64-byte transmit fifo C transparent mode C microprocessor access (no hdlc framing) inserter: tfdlck tfdl line format (ami; b8zs; hdb3) transmit pattern generator: C quasi-random: 2 20 C 1 C pseudorandom: 2 15 C 1 C ansi t1.403 bit-oriented and esf-fdl loopback codes C cept auxiliary pattern (cept = 01) C cept activate and deactivate C cept sa6 codes activate and deactivate line loopback codes transmit elastic store buffer (2 frames) receive concentration highway interface (rate adapter) chick chifs rchidata/b transmit alarm monitor: C loss of system biframe alignment C system alarm indication signal (ais) transmit signaling inserter: C ds1 robbed-bit signaling (rbs) C cept channel associated and C concentration highway access C microprocessor access common-channel signaling crc generator: multiframe encoder tnd, tpd lucent technologies inc. 15 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. pin information the package type and pin assignment for the TFRA08C13 is illustrated in figure 4. 5-6966(f) figure 4. pin assignment 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a d c b e h g f j m l k n t r p u y w v aa ad ac ab ae af a1 ball corner tfra08cf13 352-pin pbga preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 16 lucent technologies inc. lucent technologies inc. pin information (continued) table 1. pin assignments for 352-pin pbga by pin number order pin signal name pin signal name pin signal name pin signal name a1 nc b13 nc c25 nc f3 rfrmclk1 a2 nc b14 nc c26 nc f4 nc a3 nc b15 nc d1 tchidata1 f23 nc a4 rchidatab1 b16 nc d2 tfs1 f24 nc a5 rnd8 b17 nc d3 tchidatab1 f25 lopllclk a6 nc b18 3-state d4 nc f26 ds1/cept 7 a7 rchidata8 b19 rnd7 d5 pllck1 g1 tpd1 a8 tssfs8 b20 rchidatab7 d6 nc g2 tnd1 a9 tchidatab8 b21 tcrcmfs7 d7 pllck8 g3 v ss a10 rcrcmfs8 b22 tchidata7 d8 tfdl8 g4 rfrmdata1 a11 rfrmck8 b23 rcrcmfs7 d9 nc g23 lorlck a12 tpd8 b24 rfs7 d10 rfdlck8 g24 rlck7 a13 v ssd b25 nc d11 nc g25 div-pllck a14 v ddd b26 nc d12 rfrmdata8 g26 pllck-epll a15 nc c1 tssfs1 d13 nc h1 nc a16 nc c2 tcrcmfs1 d14 nc h2 rlck1 a17 nc c3 nc d15 nc h3 tck a18 v ss c4 nc d16 nc h4 nc a19 chifs c5 rchidata1 d17 v dda h23 div-rlck a20 pllck7 c6 rnd1 d18 chick h24 chick-epll a21 rchidata7 c7 v ss d19 nc h25 rnd6 a22 tssfs7 c8 rchidatab 8 d20 tfdlck7 h26 div-chick a23 rfdl7 c9 tcrcmfs8 d21 nc j1 tdi a24 rssfs7 c10 tchidata8 d22 tchidatab7 j2 trst a25 rfrmdata7 c11 rssfs8 d23 nc j3 v ss a26 nc c12 tlck8 d24 rfrmclk7 j4 ds1/cept 1 b1 tfdlck1 c13 rlck8 d25 nc j23 nc b2 nc c14 nc d26 nc j24 div-chick b3 tfdl1 c15 nc e1 rssfs1 j25 nc b4 rpd1 c16 nc e2 rfdl1 j26 rpd6 b5 rpd8 c17 v ssa e3 rcrcmfs1 k1 tdo b6 nc c18 nc e4 rfdlck1 k2 tms b7 tfdlck8 c19 reset e23 tlck7 k3 rpd2 b8 tfs8 c20 rpd7 e24 v dd k4 v dd b9 rfdl8 c21 tfdl7 e25 tpd7 k23 pllck6 b10 rfs8 c22 tfs7 e26 tnd7 k24 v ss b11 tnd8 c23 rfdlck7 f1 tlck1 k25 v dd b12 ds1/cept 8 c24 nc f2 rfs1 k26 nc l1 pllck2 r25 tnd6 y23 tchidatab5 ac19 tpd4 l2 rnd2 r26 tlck6 y24 tfdl5 ac20 ds1/cept 5 lucent technologies inc. 17 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. pin information (continued) table 1. pin assignments for 352-pin pbga by pin number order (continued) pin signal name pin signal name pin signal name pin signal name l3 rchidata2 t1 rfrmclk2 y25 tcrcmfs5 ac21 nc l4 nc t2 rfs2 y26 tfdlck5 ac22 nc l23 nc t3 nc aa1 tssfs3 ac23 nc l24 nc t4 nc aa2 tfdlck3 ac24 rfrmdata5 l25 tfdlck6 t23 nc aa3 rfdl3 ac25 rfrmclk5 l26 rchidata6 t24 rfrmclk6 aa4 nc ac26 rfs5 m1 rchidatab2 t25 ds1/cept 6aa23nc ad1nc m2 v dd t26 tpd6 aa24 tfs5 ad2 rfrmdata3 m3 tssfs2 u1 tpd2 aa25 tchidata5 ad3 nc m4 tfdlck2 u2 tnd2 aa26 tssfs5 ad4 tpd3 m23 rchidatab6 u3 v dd ab1 tchidata3 ad5 a1 m24 tfdl6 u4 rlck2 ab2 tchidatab3 ad6 a4 m25 tfs6 u23 ale _as ab3 rfs3 ad7 a8 m26 tcrcmfs6 u24 rlck6 ab4 rcrcmfs3 ad8 interrupt n1 tcrcmfs2 u25 cs ab23 rcrcmfs5 ad9 rnd4 n2 tfdl2 u26 rd _rw ab24 rfdlck5 ad10 rchidata4 n3 rfdl2 v1 ds1/cept 2 ab25 rssfs5 ad11 tssfs4 n4 nc v2 nc ab26 rfdl5 ad12 ad0 n23 rfdl6 v3 pllck3 ac1 rssfs3 ad13 ad4 n24 tssfs6 v4 nc ac2 rfdlck3 ad14 nc n25 rfdlck6 v23 rchidatab5 ac3 nc ad15 nc n26 tchidata6 v24 wr _ds ac4 nc ad16 rcrcmfs4 p1 tchidata2 v25 rnd5 ac5 a0 ad17 rfrmclk4 p2 tfs2 v26 rdy_dtack ac6 nc ad18 v dd p3 rcrcmfs2 w1 rpd3 ac7 a3 ad19 ds1/cept 4 p4 tchidatab2 w2 rnd3 ac8 nc ad20 v ss p23 nc w3 tfdl3 ac9 a10 ad21 nc p24 tchidatab6 w4 rchidatab3 ac10 pllck4 ad22 nc p25 rfrmdata6 w23 nc ac11 nc ad23 nc p26 rssfs6 w24 rpd5 ac12 tchidatab4 ad24 nc r1 rssfs2 w25 rchidata5 ac13 nc ad25 nc r2 rfdlck2 w26 pllck5 ac14 ad2 ad26 v ss r3 rfrmdata2 y1 rchidata3 ac15 rfdl4 ae1 nc r4 tlck2 y2 v ss ac16 nc ae2 nc r23 rfs6 y3 tfs3 ac17 rfs4 ae3 tlck3 r24 rcrcmfs6 y4 tcrcmfs3 ac18 nc ae4 tnd3 preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 18 lucent technologies inc. lucent technologies inc. pin information (continued) table 1. pin assignments for 352-pin pbga by pin number order (continued) table 2 shows the list of the TFRA08C13 pins and a functional description for each. table 2. pin descriptions pin signal name pin signal name pin signal name pin signal name ae5 ds1/cept 3 ae17 rfdlck4 af3 v dd af15 ad6 ae6 a2 ae18 rfrmdata4 af4 rlck3 af16 nc ae7 a6 ae19 nc af5 v dd af17 rssfs4 ae8 a9 ae20 tnd4 af6 a5 af18 nc ae9 second ae21 v ss af7 a7 af19 tlck4 ae10 mpclk ae22 tpd5 af8 a11 af20 rlck4 ae11 rchidatab4 ae23 nc af9 mpmode af21 rlck5 ae12 tfdlck4 ae24 nc af10 rpd4 af22 tnd5 ae13 tfs4 ae25 nc af11 tfdl4 af23 nc ae14 ad1 ae26 tlck5 af12 tcrcmfs4 af24 nc ae15 ad5 af1 nc af13 tchidata4 af25 nc ae16 ad7 af2 rfrmclk3 af14 ad3 af26 nc pins symbol type * description af3, af5, ad18, k25, e24, k4, m2, u3 v dd p 3.3 v power su pp l y . 3.3 v 5%. each of these pins must be b y passed with a 0.1 m f capacitor to v ss , as close to the pin as possible. ad20, ad26, ae21, g3, k24, a18, j3, c7, y2 v ss g ground. d17 v dda p 3.3 v quiet analo g power su pp l y . this pin must be b y passed with a 0.1 m f capacitor to v ssa , as close to the pin as possible. in addition, this pin should be isolated from the 3.3 v power plane with an inductive bead. c17 v ssa g 3.3 v quiet analo g ground. a14 v ddd p 3.3 v quiet di g ital power su pp l y . this pin must be b y passed with a 0.1 m f capacitor to v ssd , as close to the pin as possible. in addition, this pin should be isolated from the 3.3 v power plane with an inductive bead. a13 v ssd g 3.3 v quiet di g ital ground. b18 3-state i u 3-state ( active-low ) . assertin g this pin low forces the channel outputs into a hi g h-impedance state. c19 reset ? i u reset ( active-low ) . assertin g this pin low resets all channels on the entire device. * i u indicates an internal pull-up, i d indicates an internal pull-down. ? after reset is deasserted, the channel is in the default framing mode, as a function of the ds1/cept pin. ? asserting this pin low will initially force rdy to a low state. lucent technologies inc. 19 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. pins symbol type * description ae9 second o second pulse. a one second timer with an active-hi g h pulse. the duration of the pulse is one rlck c y cle. framer_1s receive line clock si g nal ( rlck1 ) is the default clock source for the internal second pulse timer. the internal second pulse is retimed in the individual framer sec- tions with their correspondin g receive line clock si g nal rlck. when lorlck_ ( n ) is active, then framer_ ( n + 1 ) s receive line clock si g nal is used as the clock si g nal source for the internal second pulse timer. the second pulse is used for performance monitorin g . d18 chick i chi clock. 2.048 mhz, 4.096 mhz, or 8.192 mhz. a19 chifs i chi frame s y nc. chi 8 khz input frame s y nchronization pulse. pulse width must be a minimum of one clock period of chick and a maxi- mum of a 50% dut y c y cle s q uare wave. h24 chick-epll o error phase-lock loo p si g nal. the error si g nal proportional to the phase difference between div-chick and div-rlck as detected from the internal pll circuitr y ( see table 66. global control re g ister ( greg8 ) ( 008 ) g25 div-pllck o divided-down pllck clock. 32 khz or 8 khz clock si g nal derived from the pllck input si g nal ( see table 150. chi common control re g ister ( frm_pr45 ) ( y8d )) . g26 pllck-epll o error phase-lock loo p si g nal. the error si g nal proportional to the phase difference between div-pllck and div-chick as detected b y the internal pll circuitr y ( refer to the phase-lock loop section ) . h23 div-rlck o divided-down receive line clock. 8 khz clock si g nal derived from the recovered receive line interface unit clock or the rlck input si g nal. the choice of which receive framer clock to use is defined in table 66. global control re g ister ( greg8 ) ( 008 ) . h26, j24 div-chick o divided-down chi clock. 8 khz clock si g nal derived from the transmit chi clock input si g nal ( see table 66. global control re g ister ( greg8 ) ( 008 )) . j4 ds1/cept [1 ] i u ds1/cept . strap to v dd to enable ds1 operation in the framer unit. strap to v ss to enable cept operation in the framer unit. v1 ds1/cept [2 ] ae5 ds1/cept [3 ] ad19 ds1/cept [4 ] ac20 ds1/cept [5 ] t25 ds1/cept [6 ] f26 ds1/cept [7 ] b12 ds1/cept [8 ] * i u indicates an internal pull-up, i d indicates an internal pull-down. ? after reset is deasserted, the channel is in the default framing mode, as a function of the ds1/cept pin. ? asserting this pin low will initially force rdy to a low state. pin information (continued) table 2. pin descriptions (continued) preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 20 lucent technologies inc. lucent technologies inc. pin information (continued) table 2. pin descriptions (continued) pins symbol type * description d5 pllck [1 ] i transmit framer phase-locked line interface clock. clock si g nal used to time the transmit framer. this si g nal must be phase-locked to chick clock si g nal. in ds1 frame formats, pllck can be a low- fre q uenc y si g nal ( 1.544 mhz ) or a hi g h fre q uenc y si g nal ( 6.176 mhz ) . in cept frame formats, pllck can be a low-fre q uenc y si g nal ( 2.048 mhz ) or a hi g h-fre q uenc y si g nal ( 8.192 mhz ) . l1 pllck [2 ] v3 pllck [3 ] ac10 pllck [4 ] w26 pllck [5 ] k23 pllck [6 ] a20 pllck [7 ] d7 pllck [8 ] f25 lopllck o loss of pllck clock. this pin is asserted hi g h when the pllck clock does not to gg le for a 250 s interval. this pin is deasserted 250 m s after the first ed g e of pllck ( see table 66. global control re g - ister ( greg8 ) ( 008 )) . f1 tlck [1 ] o transmit framer line interface clock. optional 1.544 mhz ds1 or 2.048 mhz output signal from the transmit framer . tnd and tpd data chan g es on the risin g ed g e of tlck. r4 tlck [2 ] ae3 tlck [3 ] af19 tlck [4 ] ae26 tlck [5 ] r26 tlck [6 ] e23 tlck [7 ] c12 tlck [8 ] g1 tpd [1 ] o transmit line interface positive-rail data. this si g nal is the transmit framer positive nrz output data. data chan g es on the risin g ed g e of tlck. in the sin g le-rail mode, tpd = transmit framer data. u1 tpd [2 ] ad4 tpd [3 ] ac19 tpd [4 ] ae22 tpd [5 ] t26 tpd [6 ] e25 tpd [7 ] a12 tpd [8 ] g2 tnd [1 ] o transmit line interface ne g ative-rail data. this si g nal is the trans- mit framer ne g ative nrz output data. data chan g es on the risin g ed g e of tlck. in the sin g le-rail mode, tnd = 0. u2 tnd [2 ] ae4 tnd [3 ] ae20 tnd [4 ] af22 tnd [5 ] r25 tnd [6 ] e26 tnd [7 ] b11 tnd [8 ] * i u indicates an internal pull-up, i d indicates an internal pull-down. ? after reset is deasserted, the channel is in the default framing mode, as a function of the ds1/cept pin. ? asserting this pin low will initially force rdy to a low state. lucent technologies inc. 21 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. pins symbol type * description d2 tfs[1 ] o transmit framer frame s y nc. this si g nal is the 8 khz frame s y nchro- nization pulse in the transmit framer. this si g nal is active-hi g h. p2 tfs[2 ] y3 tfs[3 ] ae13 tfs[4 ] aa24 tfs[5 ] m25 tfs[6 ] c22 tfs[7 ] b8 tfs[8 ] b1 tfdlck[1 ] o transmit facilit y data link clock. in ds1-dds with data link access, this is an 8 khz clock si g nal; otherwise, 4 khz. the transmit frame latches data link bits on the fallin g ed g e of tfdlck. m4 tfdlck[2 ] aa2 tfdlck[3 ] ae12 tfdlck[4 ] y26 tfdlck[5 ] l25 tfdlck[6 ] d20 tfdlck[7 ] b7 tfdlck[8 ] b3 tfdl[1 ] i transmit facilit y data link. optional serial input facilit y data link bit stream inserted into the transmit line data stream b y the transmit framer. in ds1-dds with data link access, this is an 8 kbits/s si g nal; otherwise, 4 kbits/s. in the cept frame format, tfdl can be pro- g rammed to one of the xsa bits of the not fas frame time slot 0. n2 tfdl[2 ] w3 tfdl[3 ] af11 tfdl[4 ] y24 tfdl[5 ] m24 tfdl[6 ] c21 tfdl[7 ] d8 tfdl[8 ] c5 rchidata[1 ] i receive chi data. serial input s y stem data at 2.048 mbits/s, 4.096 mbits/s, or 8.192 mbits/s. l3 rchidata[2 ] y1 rchidata[3 ] ad10 rchidata[4 ] w25 rchidata[5 ] l26 rchidata[6 ] a21 rchidata[7 ] a7 rchidata[8 ] * i u indicates an internal pull-up, i d indicates an internal pull-down. ? after reset is deasserted, the channel is in the default framing mode, as a function of the ds1/cept pin. ? asserting this pin low will initially force rdy to a low state. pin information (continued) table 2. pin descriptions (continued) preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 22 lucent technologies inc. lucent technologies inc. pin information (continued) table 2. pin descriptions (continued) pins symbol type * description a4 rchidatab [1 ] i receive chi data b. serial input s y stem data at 2.048 mbits/s, 4.096 mbits/s, or 8.192 mbits/s. m1 rchidatab [2 ] w4 rchidatab [3 ] ae11 rchidatab [4 ] v23 rchidatab [5 ] m23 rchidatab [6 ] b20 rchidatab [7 ] c8 rchidatab [8 ] g23 lorlck o loss of receive clock. this pin is asserted hi g h ( lo g ic 1 ) when rlck in the receive framer does not to gg le for a 250 m s interval. once asserted, this si g nal is deasserted on the first ed g e of rlck ( see table 66. global control re g ister ( greg8 ) ( 008 )) . h2 rlck[1 ] i receive framer line interface clock. this is the 1.544 mhz ds1 or 2.048 mhz input clock signal used by the receive framer to latch rpd and rnd data. u4 rlck[2 ] af4 rlck[3 ] af20 rlck[4 ] af21 rlck[5 ] u24 rlck[6 ] g24 rlck[7 ] c13 rlck[8 ] b4 rpd [1 ] i receive positive-rail data. nrz serial data latched by the rising edge of rlck. data rates: ds1 - 1.544 mbits/s; cept - 2.048 mbits/s. optional single-rail nrz receive data latched by the rising edge of rlck. k3 rpd [2 ] w1 rpd [3 ] af10 rpd [4 ] w24 rpd [5 ] j26 rpd [6 ] c20 rpd [7 ] b5 rp8 1 ] c6 rnd [1 ] i receive negative-rail data. nonreturn-to-zero (nrz) serial data latched by the rising edge of rlck. data rates: ds1 - 1.544 mbits/s; cept - 2.048 mbits/s. in the sin g le-rail mode, when rnd = 1 the receive bipolar violation counter increments once for each risin g ed g e of rlck. l2 rnd [2 ] w2 rnd [3 ] ad9 rn [ 4 ] v25 rnd [5 ] h25 rnd [6 ] b19 rnd [7 ] a5 rnd [8 ] * i u indicates an internal pull-up, i d indicates an internal pull-down. ? after reset is deasserted, the channel is in the default framing mode, as a function of the ds1/cept pin. ? asserting this pin low will initially force rdy to a low state. lucent technologies inc. 23 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. pins symbol type * description f3 rfrmck[1 ] o receive framer clock. output receive framer clock si g nal used to clock out the receive framer output si g nals. in normal operation, this is the recovered receive line clock si g nal. t1 rfrmck[2 ] af2 rfrmck[3 ] ad17 rfrmck[4 ] ac25 rfrmck[5 ] t24 rfrmck[6 ] d24 rfrmck[7 ] a11 rfrmck[8 ] g4 rfrmdata[1 ] o receive framer data. this si g nal is the decoded data input to the receive elastic store. durin g loss of frame ali g nment, this si g nal is forced to 1. r3 rfrmdata[2 ] ad2 rfrmdata[3 ] ae18 rfrmdata[4 ] ac24 rfrmdata[5 ] p25 rfrmdata[6 ] a25 rfrmdata[7 ] d12 rfrmdata[8 ] f2 rfs[1 ] o receive frame s y nc. this active-hi g h si g nal is the 8 khz frame s y n- chronization pulse g enerated b y the receive framer. durin g loss of frame ali g nment and si g nalin g superframe or multiframe ali g nment, this si g nal is forced to 0. t2 rfs[2 ] ab3 rfs[3 ] ac17 rfs[4 ] ac26 rfs[5 ] r23 rfs[6 ] b24 rfs[7 ] b10 rfs[8 ] e4 rfdlck[1 ] o receive facilit y data link clock. in ds1-dds with data link access, this is an 8 khz clock si g nal. otherwise, this is a 4 khz clock si g nal. the receive data link bit chan g es on the fallin g ed g e of rfdlck. r2 rfdlck[2 ] ac2 rfdlck[3 ] ae17 rfdlck[4 ] ab24 rfdlck[5 ] n25 rfdlck[6 ] c23 rfdlck[7 ] d10 rfdlck[8 ] * i u indicates an internal pull-up, i d indicates an internal pull-down. ? after reset is deasserted, the channel is in the default framing mode, as a function of the ds1/cept pin. ? asserting this pin low will initially force rdy to a low state. pin information (continued) table 2. pin descriptions (continued) preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 24 lucent technologies inc. lucent technologies inc. pin information (continued) table 2. pin descriptions (continued) pins symbol type * description e2 rfdl[1 ] o receive facilit y data link. serial output facilit y data link bit stream extracted from the receive line data stream b y the receive framer. in ds1-dds with data link access, this is an 8 kbits/s si g nal; otherwise, 4 kbits/s. in the cept frame format, rfdl can be pro g rammed to one of the rsa bits of the not fas frame ts0. durin g loss of frame ali g n- ment, this si g nal is 1. n3 rfdl[2 ] aa3 rfdl[3 ] ac15 rfdl[4 ] ab26 rfdl[5 ] n23 rfdl[6 ] a23 rfdl[7 ] b9 rfdl[8 ] d1 tchidata[1 ] o transmit chi data. serial output s y stem data at 2.048 mbits/s, 4.096 mbits/s, or 8.192 mbits/s. this port is forced into a hi g h-imped- ance state for all inactive time slots. p1 tchidata[2 ] ab1 tchidata[3 ] af13 tchidata[4 ] aa25 tchidata[5 ] n26 tchidata[6 ] b22 tchidata[7 ] c10 tchidata[8 ] d3 tchidatab[1 ] o transmit chi data b. serial output s y stem data at 2.048 mbits/s, 4.096 mbits/s, or 8.192 mbits/s. this port is forced into a hi g h-imped- ance state for all inactive time slots. p4 tchidatab[2 ] ab2 tchidatab[3 ] ac12 tchidatab[4 ] y23 tchidatab[5 ] p24 tchidatab[6 ] d22 tchidatab[7 ] a9 tchidatab[8 ] e1 rssfs [1 ] o receive framer si g nalin g su p erframe s y nc. this active-hi g h si g nal is the cept si g nalin g superframe ( multiframe ) s y nchronization pulse in the receive framer. r1 rssfs [2 ] ac1 rssfs [3 ] af17 rssfs [4 ] ab25 rssfs [5 ] p26 rssfs [6 ] a24 rssfs [7 ] c11 rssfs [8 ] * i u indicates an internal pull-up, i d indicates an internal pull-down. ? after reset is deasserted, the channel is in the default framing mode, as a function of the ds1/cept pin. ? asserting this pin low will initially force rdy to a low state. lucent technologies inc. 25 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. e3 rcrcmfs [1 ] o receive framer crc-4 multiframe s y nc. this active-hi g h si g nal is the cept crc-4 multiframe s y nchronization pulse in the receive framer. p3 rcrcmfs [2 ] ab4 rcrcmfs [3 ] ad16 rcrcmfs [4 ] ab23 rcrcmfs [5 ] r24 rcrcmfs [6 ] b23 rcrcmfs [7 ] a10 rcrcmfs [8 ] c1 tssfs [1 ] o transmit framer si g nalin g su p erframe s y nc. this si g nal is the cept si g nalin g superframe ( multiframe ) s y nchronization pulse in the transmit framer. this si g nal is active-hi g h. m3 tssfs [2 ] aa1 tssfs [3 ] ad11 tssfs [4 ] aa26 tssfs [5 ] n24 tssfs [6 ] a22 tssfs [7 ] a8 tssfs [8 ] c2 tcrcmfs [1 ] o transmit framer crc-4 multiframe s y nc. this si g nal is the cept crc-4 submultiframe s y nchronization pulse in the transmit framer. this si g nal is active-hi g h. n1 tcrcmfs [2 ] y4 tcrcmfs [3 ] af12 tcrcmfs [4 ] y25 tcrcmfs [5 ] m26 tcrcmfs [6 ] b21 tcrcmfs [7 ] c9 tcrcmfs [8 ] af9 mpmode i u mpmode. strap to ground to enable the motorola 68360 microproces- sor protocol (mode1). strap to v dd to enable the intel 80x86/88 micro- processor protocol (mode3). u26 rd _r/w i read ( active-low ) . in the intel interface mode, the TFRA08C13 drives the data bus with the contents of the addressed re g ister while rd is low. read/write . in the motorola interface mode, this si g nal is asserted hi g h for read accesses; this pin is asserted low for write accesses. * i u indicates an internal pull-up, i d indicates an internal pull-down. ? after reset is deasserted, the channel is in the default framing mode, as a function of the ds1/cept pin. ? asserting this pin low will initially force rdy to a low state. pin information (continued) table 2. pin descriptions (continued) preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 26 lucent technologies inc. lucent technologies inc. pin information (continued) table 2. pin descriptions (continued) pins symbol type * description v24 wr _ds i write ( active-low ) . in the intel mode, the value present on the data bus is latched into the addressed re g ister on the positive ed g e of the si g nal applied to wr . data strobe ( active-low ) . in the motorola mode, when as is low and r/w is low ( write ) , the value present on the data bus is latched into the addressed re g ister on the positive ed g e of the si g nal applied to ds ; when as is low and r/w is hi g h ( read ) , the TFRA08C13 drives the data bus with the contents of the addressed re g ister while ds is low. u25 cs ? i chi p select ( active-low ) . in the intel interface mode, this pin must be asserted low to initiate a read or write access and kept low for the dura- tion of the access; assertin g cs low forces rdy out of its hi g h-imped- ance state into a 0 state. u23 ale _as i address strobe ( active-low ) . in the motorola interface mode, this pin must be asserted low to initiate a read or write access and kept low for the duration of the access. ad12 d0 i/o micro p rocessor data bus. bidirectional data bus used for read and write accesses. 3-stated output. ae14 d1 ac14 d2 af14 d3 ad13 d4 ae15 d5 af15 d6 ae16 d7 ac5 a0 i micro p rocessor address bus. address bus used to access the inter- nal re g isters. ad5 a1 ae6 a2 ac7 a3 ad6 a4 af6 a5 ae7 a6 af7 a7 ad7 a8 ae8 a9 ac9 a10 af8 a11 * i u indicates an internal pull-up, i d indicates an internal pull-down. ? after reset is deasserted, the channel is in the default framing mode, as a function of the ds1/cept pin. ? asserting this pin low will initially force rdy to a low state. lucent technologies inc. 27 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. pin information (continued) table 2. pin descriptions (continued) pins symbol type * description ad8 interrupt o interru p t. interrupt is asserted hi g h/low indicatin g an internal inter- rupt condition/event has been g enerated. interrupt events/conditions are maskable throu g h the control re g isters. this output can be wired- or or wired-and to an y other lo g ic output ( see table 64global control re g ister ( greg4 ) ( 004 )) . v26 rdy_dtack o read y . in the intel interface mode, this pin is asserted hi g h to indicate the completion of a read or write access; this pin is forced into a hi g h- impedance state while cs is hi g h. data transfer acknowled g e ( active-low ) . in the motorola interface mode, dtack is asserted low to indicate the completion of a read or write access; dtack is 1 otherwise. ae10 mpck i u micro p rocessor clock. microprocessor clock used in the intel mode to g enerate the ready si g nal. k1 tdo o jtag data out p ut. serial output data sampled on the fallin g ed g e of tck from the boundar y -scan test circuitr y . j1 tdi i u jtag data in p ut. serial input data sampled on the risin g ed g e of tck for the boundar y -scan test circuitr y . h3 tck i u jtag clock in p ut. tck provides the clock for the boundar y -scan test lo g ic. k2 tms i u jtag mode select ( active-hi g h ) . the si g nal values received at tms are sampled on the risin g ed g e of tck and decoded b y the boundar y - scan tap controller to control boundar y -scan test operations. j2 trst i d jtag reset in p ut ( active-low ) . assert this pin low to as y nchronousl y initialize/reset the boundar y -scan test lo g ic. * i u indicates an internal pull-up, i d indicates an internal pull-down. ? after reset is deasserted, the channel is in the default framing mode, as a function of the ds1/cept pin. ? asserting this pin low will initially force rdy to a low state. preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 28 lucent technologies inc. lucent technologies inc. pin information (continued) table 2. pin descriptions (continued) pins symbol type * description a1, a2, a3, a6, a15, a16, a17, a26, b2, b6, b13, b14, b15, b16, b17, b25, b26, c3, c4, c14, c15, c16, c18, c24, c25, c26, d4, d6, d9, d11, d13, d14, d15, d16, d19, d21, d23 d25, d26, f4, f23, f24, h1, h4, j23, j25, k26, l4, l23, l24, n4, p23, t3, t4 t23, v2, v4, w23, aa4, aa23, ac3, ac4, ac6, ac8, ac11, ac13, ac16, ac18, ac21, ac22, ac23, ad1, ad3, ad14, ad15, ad21, ad22, ad23, ad24, ad25, ae1, ae2, ae19, ae23, ae24, ae25, af1, af16, af18, af23, af24, af25, af26 nc no connection. * i u indicates an internal pull-up, i d indicates an internal pull-down. ? after reset is deasserted, the channel is in the default framing mode, as a function of the ds1/cept pin. ? asserting this pin low will initially force rdy to a low state. lucent technologies inc. 29 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. liu-framer interface liu-framer physical interface the transmit framer-liu interface for the TFRA08C13 consists of the tnd, tpd, and tlck pins. in normal opera- tions, tnd, tpd, and tlck are driven from the transmit framer and are connected to an external transmit line inter- face. the receive framer-liu interface for the TFRA08C13 consists of the rpd, rnd, and rlck internal signals. in normal operations, rnd, rpd, and rlck are sourced from an external receive line interface unit and are directly connected to the receive framer. figure 5 illustrates the interfaces of the transmit and receive framer units. 5-7169(f) figure 5. block diagram of framer line interface ttip tring external interface unit tlck tnd tpd transmit framer transmit hdlc facil it y data link interface receive concentration highway interface tfdlck tfdl rchidata chick receive hdlc facility data link interface receive framer rtip rring receive line interface unit transmit concentration highway interface tchidata rfdlck rfdl (xliu) (xfrmr) (rchi) (xchi) (rfrmr) (rliu) line interface system pllck rfrmck rlck rnd rpd transmit line rchidatab chifs external tchidatab interface preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 30 lucent technologies inc. lucent technologies inc. liu-framer interface (continued) figure 6 shows the timing requirements for the transmit and receive framer interfaces in the liu-bypass mode. 5-4558(f).dr.1 figure 6. transmit framer tlck to tnd, tpd and receive framer rnd, rpd to rlck timing 162 ns t1-ds1 648 ns t1 t2r-f t2f-r t3 t4 t5 pllck tlck tnd, tpd rlck rnd, rpd rfrmck t7 = rpd, rnd hold from rising rlck = 40 ns t6 t7 t8 t2r-f: t2f-r: pllck to tlck delay = 50 ns t3-ds1 = 648 ns t3-cept = 488 ns t4 = tlck to valid tpd, tnd = 30 ns t5-cept = 488 ns t5-ds1 = 648 ns t6 = rpd, rnd setup to rising rlck = 40 ns t8r-f: t8f-r: rlck to rfrmck delay = 50 ns bit 0 of frm_pr45 hflf = 0 hflf = 1 122 ns t1-cept 488 ns is the hflf bit lucent technologies inc. 31 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. liu-framer interface (continued) line encoding single rail the default line code is single-rail mode and single-rail function of the framer specified by frm_pr8 bit 7 = 1, bit 6 = 1, and bit 5 = 0. in this mode, the framer bipolar encoder/decoder is disabled and monitoring of received bpv errors is done with the use of the rnd input. when rnd = 1, the bpv counter increments by one on the rising edge of rlck. the transmit framer transmits data via the tpd output pin while tnd is forced to a 0 state. dual rail in dual-rail mode, the dual-rail function of the framer is selected through frm_pr8 bits 57. bipolar encoding/ decoding is enabled in the framer. noncoded/decoded data is exchanged between the liu and framer via the rpd, rnd, rclk, tpd, tnd, and tclk liu-framer interface. ds1: alternate mark inversion (ami) the default line code used for t1 applications is alternate mark inversion (ami). the coding scheme represents a 1 with a pulse or mark on the positive or negative rail and a 0 with no pulse on either rails. this scheme is shown in table 3. table 3. ami encoding the t1 ones density rule states that: in every 24 bits of information to be transmitted, there must be at least three pulses, and no more than 15 zeros may be transmitted consecutively. receive ones density is monitored by the receive line interface as per t1m1.3/93-005, itu g.775, or tr-tsy- 000009. the receive framer indicates excessive zeros upon detecting any zero string length greater than 15 contiguous zeros (no pulses on either rpd or rnd). both excessive zeros and coding violations are indicated as bipolar viola- tions. ds1: zero code suppression (zcs) zero code suppression is a technique known as pulse stuffing in which the seventh bit of each time slot is stuffed with a one. the line format (shown in table 4) limits the data rate of each time slot from 64 kbits/s to 56 kbits/s. the default zcs format stuffs the seventh bit of those all-zero time slots programmed for robbed-bit signaling (as defined in the signaling control registers with the f and g bits). input bit stream 1011 0000 0111 1010 ami data C0+C 0000 0+C+ C0+0 preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 32 lucent technologies inc. lucent technologies inc. liu-framer interface (continued) the receive framer indicates a bipolar violation upon detecting a block of 15 consecutive 0s with no ami encoding (no pulses on either rpd or rnd). when an internal bipolar violation and a violation of 15 consecutive 0s occur simultaneously, only one violation is indicated. table 4. ds1 zcs encoding ds1: binary 8 zero code suppression (b8zs) clear channel transmission can be accomplished using binary 8 zero code suppression (b8zs). eight consecutive 0s are replaced with the b8zs code. this code consists of two bipolar violations in bit position 4 and 7 and valid bipolar marks in bit positions 5 and 8. the receiving end recognizes this code and replaces it with the original string of eight 0s. the receive framer indicates excessive zeros upon detecting a block of eight or more consecutive 0s. (no pulses on either rpd or rnd). both excessive zeros and coding violations are indicated as bipolar violations. table 5 shows the encoding of a string of 0s using b8zs. b8zs is recommended when esf format is used. v rep- resents a violation of the bipolar rule and b represents an inserted pulse conforming to the ami rule. table 5. ds1 b8zs encoding * bits 56 represent a bipolar violation pair. bipolar violation with respect to the last previous 1 bit. input bit stream 00000000 01010000 00000000 00000000 zcs data (framer mode) 00000010 01010010 00000010 00000010 default zcs 00000010 01010000 00000000 ( data time slot remains clear ) 00000010 bit positions 1234567812345678 before b8zs 0000000010100000000 after b8zs* 0 00vb0vbb0b00 0vb0vb lucent technologies inc. 33 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. liu-framer interface (continued) cept: high-density bipolar of order 3 (hdb3) the line code used for cept is described in itu rec. g.703 section 6.1 as high-density bipolar of order 3 (hdb3). hdb3 uses a substitution code that acts on strings of four zeros. the substitute hdb3 codes are 000v and b00v, where v represents a violation of the bipolar rule and b represents an inserted pulse conforming to the ami rule defined in itu rec. g.701, item 9004. the choice of the b00v or 000v is made so that the number of b pulses between consecutive v pulses is odd. in other words, successive v pulses are of alternate polarity so that no direct current (dc) component is introduced. the substitute codes follow each other if the string of zeros continues. the choice of the first substitute code is arbitrary. a line code error consists of two pulses of the same polarity that is not defined as one of the two substitute codes. excessive zeros consists of any zero string length greater than four contiguous zeros. both excessive zeros and coding violations are indicated as bipolar violations. an example is shown in table 6. table 6. ituhdb3 coding input bit stream 1011 0000 01 0000 0000 0000 0000 hdb3-coded data 1011 000v 01 000v b00v b00v b00v hdb3-coded levels C0+C 000C 0+ 000+ C00C +00+ C00C hdb3 with 5 double bpvs C0+C C000 0+ +00+ 0CC C +00+ C00C 1-bpv 3-bpv 5-bpv preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 34 lucent technologies inc. lucent technologies inc. frame formats the supported north american t1 framing formats are superframe (d4, slc -96, and digital data service-dds) and extended superframe (esf). the device can be programmed to support the itu-cept-e1 basic format with and without crc-4 multiframe formatting. this section describes these framing formats. t1 framing structures t1 is a digital transmission system which multiplexes twenty-four 64 kbits/s time slots (ds0) onto a serial link. the t1 system is the lowest level of hierarchy on the north american t-carrier system, as shown in figure 7 table 7. t-carrier hierarchy frame, superframe, and extended superframe definitions each time slot (ds0) is an assembly of 8 bits sampled every 125 s. the data rate is 64 kbits/s and the sample rate is 8 khz. time-division multiplexing 24 ds0 time slots together produces a 192-bit (24 ds0s) frame. a framing bit is added to the beginning of each frame to allow for detection of frame boundaries and the transport of additional maintenance information. this 193-bit frame, also referred to as a ds1 frame, is repeated every 125 s to yield the 1.544 mbits/s t1 data rate.ds1 frames are bundled together to form superframes or extended superframes. 5-4559(f).br.1 figure 7. t1 frame structure t carrier ds0 channels bit rate (mbits/s) digital signal level t1 24 1.544 ds1 t1-c 48 3.152 ds1c t2 96 6.312 ds2 t3 672 44.736 ds3 t4 4032 274.176 ds4 frame 1 frame 2 frame 3 frame 24 frame 23 frame 1 frame 2 frame 11 frame 12 f bit time slot 1 time slot 2 time slot 24 123 45 678 24-frame extended esf = 3.0 ms 12-frame superframe sf = 1.5 ms 193-bit frame ds1 = 125 m s 8-bit time slot ds0 = 5.19 m s superframe lucent technologies inc. 35 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. frame formats (continued) transparent framing format the transmit framer can be programmed to transparently transmit 193 bits of system data to the line. the system interface must be programmed such that the stuffed time slots are 1, 5, 9, 13, 17, 21, 25, and 29 (frm_pr43 bits 20 must be set to 000) and either transparent framing mode 1 or transparent framing mode 2 is enabled (frm_pr26 bit 3 or bit 4 must be set to 1). in transparent mode 1 or mode 2, the transmit framer extracts from the receive system data bit 8 of time slot 1 and inserts this bit into the framing bit position of the transmit line data. the other 7 bits of the receive system time slot 1 are ignored by the transmit framer. the receive framer will extract the f-bit (or 193rd bit) of the receive line data and insert it into bit 7 of time slot 1 of the system data; the other bits of time slot 1 are set to 0. frame integrity is maintained in both the transmit and receive framer sections. 5-5989(f).b figure 8. t1 transparent frame structure in transparent framing mode 1, the receive framer is forced not to reframe on the receive line data. other than bipolar violations and unframed ais monitoring, there is no processing of the receive line data. the receive framer will insert the 193rd bit of the receive line data into bit 8 of time slot 1 of the transmit system data. in transparent framing mode 2, the receive framer functions normally on receive line data. all normal monitoring of receive line data is performed and data is passed to the transmit chi as programmed. the receive framer will insert the extracted framing bit of the receive line data into bit 8 of time slot 1 of the transmit system data. the remaining bits in time slot 1 are set to 0. time slot 1 (stuff time slot) 32 time-slot chi frame time slot 2 time slot 3 time slot 31 time slot 32 0000000f bit tramsmit framers 193-bit frame ds1 = 125 m s time slot 1 time slot 2 time slot 24 f bit system interface control register bits[2:0] = 000. system frame sync mask register frm_pr26 bit 3 or bit 4 = 1. frame integrity is maintained with f bit and the system payload. preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 36 lucent technologies inc. lucent technologies inc. frame formats (continued) d4 frame format d4 superframe format consists of 12 ds1 frames. table 8 shows the structure of the d4 superframe. table 8. d4 superframe format 1. frame 1 is transmitted first. 2. following ansi t1.403, the bits are numbered 02315. bit 0 is transmitted first. bits in each ds0 time slot are numbered 1 through 8, and bit 1 of each ds0 is transmitted first. 3. the remote alarm forces bit 2 of each time slot to a 0-state when enabled. the japanese remote alarm forces framing bit 12 ( bit number 2123) to a 1-state when enabled. 4. signaling option none uses bit 8 for traffic data. 5. frames 6 and 12 contain the robbed-bit signaling information in bit 8 of each voice channel, when enabled. the receive framer uses both the f t and f s framing bits during its frame alignment procedure. frame number 1 framing bits bit used in each time slot signaling options bit number 2 terminal frame f t signal frame f s traffic (all channels) remote alarm 3 signaling none 4 2-state 4-state 101182 21930182 33860182 45790182 57721182 6 5 965 1 17 2 8 a a 7 1158 0 18 2 8 1351 1 18 2 9 1544 1 18 2 10 1737 1 18 2 11 1930 0 18 2 12 5 2123 0 17 2 8 a b lucent technologies inc. 37 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. frame formats (continued) digital data service (dds) frame format the superframe format for dds is the same as that given for d4. dds is intended to be used for data-only traffic, and as such, the system should ensure that the framer is in the nonsignaling mode. dds uses time slot 24 (fas channel) to transmit the remote frame alarm and data link bits. the format for time slot 24 is shown in table 9. the facility data link timing is shown in figure 9 below. table 9. dds channel-24 format 5-3910(f).cr.1 figure 9. t7633 facility data link access timing of the transmit and receive framer sections slc -96 frame format slc -96 superframe format consists of 12 ds1 frames similar to d4. the f t pattern is exactly the same as d4. the f s pattern uses that same structure as d4 but also incorporates a 24-bit data link word as shown below. 5-6421(f)r.1 . figure 10. slc- 96 frame format time slot 24 = 10111yd0 y = (bit 6) remote frame alarm: 1 = no alarm state; 0 = alarm state d = (bit 7) data link bits (8 kbits/s) t8 t9 t9 t10 t11 t8: tfdlck cycle = t9: tfdl to tfdlck setup/hold = 40 ns t10: rfdlck cycle = t11: rfdlck to rfdl delay = 40 ns tfdlck tfdl rfdlck rfdl 250 m s (all other modes) 125 m s (dds) 250 m s (all other modes) 125 m s (dds) slc -96 36-frame d-bit superframe interval (72 ds1 frames) sslc -96 24-bit data link word fs = frame n frame n + 1 . . . 000111000111d 1 ddddddddddddddddddddddd 24 000111000111ddd . . . frame n + 2 frame n + 3 frame n + 4 frame n + 5 frame n + 6 frame n + 7 frame n + 8 frame n C 1 preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 38 lucent technologies inc. lucent technologies inc. frame formats (continued) external tfdl source. data may be inserted and extracted from the slc -96 data link from either the external facility data link (tfdl) ports or the slc -96 data stack. source selection is controlled by frm_pr21 bit 6 and frm_pr29 bit 5bit 7. the transmit framer synchronizes on tfdl = 000111000111 . . . and forces a superframe boundary based on this pattern. when sourcing an external bit stream, it is the systems responsibility to ensure that tfdl data contain the pattern of 000111000111 . . . . the d pattern sequence is shown in table 10. table 11 shows the encoding for the line switch field. table 10. slc -96 data link block format data link block bit definition bit value d 1 (leftmost bit) c 1 concentrator bit 0 or 1 d 2 c 2 concentrator bit 0 or 1 d 3 c 3 concentrator bit 0 or 1 d 4 c 4 concentrator bit 0 or 1 d 5 c 5 concentrator bit 0 or 1 d 6 c 6 concentrator bit 0 or 1 d 7 c 7 concentrator bit 0 or 1 d 8 c 8 concentrator bit 0 or 1 d 9 c 9 concentrator bit 0 or 1 d 10 c 10 concentrator bit 0 or 1 d 11 c 11 concentrator bit 0 or 1 d 12 spoiler bit 1 0 d 13 spoiler bit 2 1 d 14 spoiler bit 3 0 d 15 m 1 maintenance bit 0 or 1 d 16 m 2 maintenance bit 0 or 1 d 17 m 3 maintenance bit 0 or 1 d 18 a1alarm bit 0 or 1 d 19 a2alarm bit 0 or 1 d 20 s 1 line-switch bit defined in table 11 d 21 s 2 line-switch bit defined in table 11 d 22 s 3 line-switch bit defined in table 11 d 23 s 4 line-switch bit defined in table 11 d 24 (rightmost bit) spoiler bit 4 1 lucent technologies inc. 39 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. frame formats (continued) table 11 . slc -96 line switch message codes internal slc -96 stack source. optionally, a slc -96 fdl stack may be used to insert and correspondingly extract the fdl information in the slc -96 frame format. the transmit slc -96 fdl bits are sourced from the transmit framer slc -96 fdl stack. the slc -96 fdl stack (see frm_pr31frm_pr35) consists of five 8-bit registers that contain the slc -96 fs and d-bit information as shown in table 12. the transmit stack data is transmitted to the line when the stack enable mode is active in the parameter registers frm_pr21 bit 6 = 1 and frm_pr29 bit 5bit 7 = x10 (binary). the receive slc -96 stack data is received when the receive framer is in the superframe alignment state. in the slc -96 mode, while in the loss of superframe alignment (lsfa) state, updating of the receive framer slc -96 stack is halted and neither the receive stack interrupt nor receive stack flag are asserted. table 12. transmit and receive slc -96 stack structure bit 5bit 0 of the first 2 bytes of the slc -96 fdl stack in table 12 are transmitted to the line as the slc -96 f s sequence. bit 7 of the third stack register is transmitted as the c 1 bit of the slc -96 d sequence. the spoiler bits (spb1, spb2, spb3, and spb4) are taken directly from the transmit stack. the protocol for accessing the slc -96 stack information for the transmit and receive framer is described below. the transmit slc -96 stack must be written with valid data when transmitting stack data. the device indicates that it is ready for an update of its transmit stack by setting register frm_sr4 bit 5 ( slc -96 transmit fdl stack ready) high. at this time, the system has about 9 ms to update the stack. data written to the stack during this interval will be transmitted during the next slc -96 superframe d-bit interval. by reading bit 5 in register sr4, the system clears this bit so that it can indicate the next time the transmit stack is ready. if the trans- mit stack is not updated, then the content of the stack is retransmitted to the line. the start of the slc -96 36-frame f s interval of the transmit framer is a function of the first 2 bytes of the slc -96 transmit stack registers. these bytes must be programmed as shown in table 12. programming any other state into these two registers disables the proper transmission of the slc -96 d bits. once programmed correctly, the transmit slc -96 d-bit stack is trans- mitted synchronous to the transmit slc -96 superframe structure. on the receive side, the device indicates that it has received data in the receive fdl stack (registers frm_sr54 frm_sr58) by setting bit 4 in register frm_sr4 ( slc -96 receive fdl stack ready) high. the system then has about 9 ms to read the content of the stack before it is updated again (old data lost). by reading bit 4 in register frm_sr4, the system clears this bit so that it can indicate the next time the receive stack is ready. as explained above, the slc -96 receive stack is not updated when superframe alignment is lost. s 1 s 2 s 3 s 4 code definition 1111 idle 1 1 1 0 switch line a receive 1 1 0 1 switch line b transmit 1 1 0 0 switch line c transmit 1 0 1 0 switch line d transmit 0 1 0 1 switch line b transmit and receive 0 1 0 0 switch line b transmit and receive 0 0 1 0 switch line b transmit and receive register number bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) 1 (lsr) 0 000011 1 2 0 000011 1 3c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 8 4c 9 c 10 c 11 spb 1 = 0 spb 2 = 1 spb 3 = 0 m 1 m 2 5m 3 a 1 a 2 s 1 s 2 s 3 s 4 spb 4 = 1 preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 40 lucent technologies inc. lucent technologies inc. frame formats (continued) extended superframe format the extended superframe format consists of 24 ds1 frames. the f bits are used for frame alignment, superframe alignment, error checking, and facility data link transport. table 13 shows the esf frame format. table 13. extended superframe (esf) structure 1. frame 1 is transmitted first. 2. the remote alarm is a repeated 1111111100000000 pattern in the dl when enabled. 3. following ansi t1.403, the bits are numbered 04361. bit 0 is transmitted first. bits in each ds0 time slot are numbered 1 through 8, and bit 1 of each ds0 is transmitted first. 4. the c 1 to c 6 bits are the cyclic redundancy check-6 (crc-6) checksum bits calculated over the previous extended superframe. 5. signaling option none uses bit 8 for traffic data. 6. frames 6, 12, 18, and 24 contain the robbed-bit signaling information in bit 8 of each voice channel, when enabled. the esf format allows for in-service error detection and diagnostics on t1 circuits. esf format consist of 24 fram- ing bits: 6 for framing synchronization (2 kbits/s); 6 for error detection (2 kbits/s); and 12 for in-service monitoring and diagnostics (4 kbits/s). frame number 1 frame bit bit use in each time slot signaling option 2 bit number 3 f e d l crc-6 4 traffic signaling none 5 2-state 4-state 16-state 1 0 d 18 2 193 c 1 18 3 386 d 18 4 579 0 18 5 772 d 18 6 6 965 c 2 17 8 a a a 7 1158 d 18 8 1351 0 18 9 1544 d 18 10 1737 c 3 18 11 1930 d 18 12 6 2123 1 17 8 a b b 13 2316 d 18 14 2509 c 4 18 15 2702 d 18 16 2895 0 18 17 3088 d 18 18 6 3281 c 5 17 8 a a c 19 3474 d 18 20 3667 1 18 21 3860 d 18 22 4053 c 6 18 23 4246 d 18 24 6 4439 1 17 8 a b d lucent technologies inc. 41 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. frame formats (continued) cyclic redundancy checking is performed over the entire esf data payload (4,608 data bits, with all 24 framing bits (f e , d l , crc-6) set to 1 during calculations). the crc-6 bits transmitted in esf will be determined as follows: n the check bits, c1 through c6, contained in esf(n + 1) will always be those associated with the contents of esf(n), the immediately preceding esf. when there is no esf immediately preceding, the check bits may be assigned any value. n for the purpose of crc-6 calculation only, every f bit in esf(n) is set to 1. esf(n) is altered in no other way. n the resulting 4632 bits of esf(n) are used, in order of occurrence, to construct a polynomial in x such that the first bit of esf(n) is the coefficient of the term x 4631 and the last bit of esf(n) is the coefficient of the term x 0 . n the polynomial is multiplied by the factor x 6 , and the result is divided, modulo 2, by the generator polynomial x 6 + x + 1. the coefficients of the remainder polynomial are used, in order of occurrence, as the ordered set of check bits, c1 through c6, that are transmitted in esf(n + 1). the ordering is such that the coefficient of the term x 5 in the remainder polynomial is check bit c1 and the coefficient of the term x 0 in the remainder polynomial is check bit c6. the esf remote frame alarm consists of a repeated eight ones followed by eight 0s transmitted in the data link position of the framing bits. t1 loss of frame alignment (lfa) loss of frame alignment condition for the superframe or the extended superframe formats is caused by the inability of the receive framer to maintain the proper sequence of frame bits. the number of errored framing bits required to detect a loss of frame alignment is given is table 14. table 14. t1 loss of frame alignment criteria the receive framer indicates the loss of frame and superframe conditions by setting the lfa and lsfa bits (frm_sr1 bit 0 and bit 1), respectively, in the status registers for the duration of the conditions. the local system may give indication of its lfa state to the remote end by transmitting a remote frame alarm (rfa). in addition, in the lfa state, the system may transmit an alarm indication signal (ais) to the system interface. format number of errored framing bits that will cause a loss of frame alignment condition d4 2 errored frame bits (f t or f s ) out of 4 consecutive frame bits if frm_pr10 bit 2 = 1. 2 errored f t bits out of 4 consecutive f t bits if prm_pr10 bit 2 = 0. slc -96 2 errored frame bits (f t or f s ) out of 4 consecutive frame bits if frm_pr10 bit 2 = 1. 2 errored f t bits out of 4 consecutive f t bits if frm_pr10 bit 2 = 0. dds: frame 3 errored frame bits (f t or f s ) or channel 24 fas pattern out of 12 consecutive frame bits. esf 2 errored f e bits out of 4 consecutive f e bits or optionally 320 or more crc-6 errored check- sums within a one second interval if loss of frame alignment due to excessive crc-6 errors is enabled in frm_pr9. preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 42 lucent technologies inc. lucent technologies inc. frame formats (continued) t1 frame recovery alignment algorithms when in a loss of frame alignment state, the receive framer searches for a new frame alignment and forces its inter- nal circuitry to this new alignment. the receive framers synchronization circuit inhibits realignment in t1 framing formats when repetitive data patterns emulate the t1 frame alignment patterns. t1 frame synchronization will not occur until all frame sequence emulating patterns disappear and only one valid pattern exists. the loss of frame alignment state will always force a loss of superframe alignment state. superframe alignment is established only after frame alignment has been determined in the d4 and slc -96 frame format. table 15 gives the requirements for establishing t1 frame and superframe alignment. table 15. t1 frame alignment procedures frame format alignment procedure d4: frame using the f t frame position as the starting point, frame alignment is established when 24 con- secutive f t and f s frame bits, excluding the twelfth f s bit, (48 total frames) are received error-free. once frame alignment is established, then superframe alignment is determined. d4: superframe after frame alignment is determined, two valid superframe bit sequences using the f s bits must be received error-free to establish superframe alignment. slc -96: frame using the f t frame position as the starting point, frame alignment is established when 24 con- secutive f t frame bits (48 total frames) are received error-free. once frame alignment is established, then superframe alignment is determined. slc -96: superframe after frame alignment is determined, superframe alignment is established on the first valid superframe bit sequence 000111000111. dds: frame using the f t frame position as the starting point, frame alignment is established when six consecutive f t /f s frame bits and the dds fas in time slot 24 are received error-free. in the dds format, there is no search for a superframe structure. esf frame and superframe alignment is established simultaneously using the f e framing bit. alignment is established when 24 consecutive f e bits are received error-free. once frame/ superframe alignment is established, the crc-6 receive monitor is enabled. lucent technologies inc. 43 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. frame formats (continued) t1 robbed-bit signaling to enable signaling, register frm_pr44 bit 0 (tsig) must be set to 0. robbed-bit signaling, used in either esf or sf framing formats, robs the eighth bit of the voice channels of every sixth frame. the signaling bits are designated a, b, c, and d, depending on the signaling format used. the robbed- bit signaling format used is defined by the state of the f and g bits in the signaling registers (see ds1: robbed-bit signaling on page 61). the received channel robbed-bit signaling format is defined by the corresponding transmit signaling f and g bits. table 16 shows the state of the transmitted signaling bits as a function of the f and g bits. table 16. robbed-bit signaling options * see register frm_pr43 bit 3 and bit 4. the robbed-bit signaling format for each of the 24 t1 transmit channels is programmed on a per-channel basis by setting the f and g bits in the transmit signaling direction. slc -96 9-state signaling slc -96 9-state signaling state is enabled by setting both the f and g bits in the signaling registers to the 0-state, setting the slc -96 signaling control register frm_pr43 bit 3 to 1, and setting register frm_pr44 bit 0 to 0. table 17 shows the state of the transmitted signaling bits to the line as a function of the a-, b-, c-, and d-bit settings in the transmit signaling registers. in table 17 below, x indicates either a 1- or a 0-state, and t indicates a toggle, transition from either 0 to 1 or 1 to 0, of the transmitted signaling bit. in the line receive direction, this signaling mode functions identically to the preceding transmit path description. table 17 . slc -96 9-state signaling format g f robbed-bit signaling format frame 6121824 0 0 esf: 16-state slc *: 9-state, 16-state abcd 01 4-state abab 1 0 data channel (no signaling) payload data 11 2-state aaaa transmit signaling register settings transmit to the line signal bits slc -96 signaling statesabcda = f(a, c)b = f(b, d) state 1 0000 0 0 state 2 0001 0 t state 3 010x 0 1 state 4 0010 t 0 state 5 0011 t t state 6 011x t 1 state 7 1 0 x 0 1 0 state 8 1 0 x 1 1 t state 9 1 1 x x 1 1 preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 44 lucent technologies inc. lucent technologies inc. frame formats (continued) 16-state signaling the default signaling mode while in slc -96 framing is 16-state signaling. slc -96 16-state signaling is enabled by setting both the f and g bits in the signaling registers to the 0 state, setting the slc -96 signaling control register frm_pr43 bit 3 and bit 4 to 0, and setting register frm_pr44 bit 0 to 0. table 18 shows the state of the transmit- ted signaling bits to the line as a function of the a-, b-, c-, and d-bit settings in the transmit signaling registers. in table 18 below, under transmit to the line signal bits, a and b are transmitted into one slc -96 12-frame signaling superframe, while a and b are transmitted into the next successive slc -96 12-frame signaling superframe. in the line receive direction, this signaling mode functions identically to the preceding transmit path description. the signaling mapping of this 16-state signaling mode is equivalent to the mapping of the slc -96 9-state signaling mode. table 18. 16-state signaling format transmit signaling register settings transmit to the line signal bits slc -96 signaling statesabcda bab state 0 00000000 state 1 00010001 state 2 00100010 state 3 00110011 state 4 01000100 state 5 01010101 state 6 01100110 state 7 01110111 state 8 10001000 state 9 10011001 state 10 10101010 state 11 10111011 state 12 11001100 state 13 11011101 state 14 11101110 state 15 11111111 lucent technologies inc. 45 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. frame formats (continued) cept 2.048 basic frame, crc-4 time slot 0, and signaling time slot 16 multiframe structures as defined in tu rec. g.704, the cept 2.048 frame, crc-4 multiframe, and channel associated signaling multi- frame structures are illustrated in figure 11 5-4548(f).cr.1 figure 11. itu 2.048 basic frame, crc-4 multiframe, and channel associated signaling multiframe structures 0 1 a s a4 s a5 s a6 s a7 s a8 c 1 0 0 1 1 0 1 1 c 2 0 0 1 1 0 1 1 0 1 a s a4 s a5 s a6 s a7 s a8 c 3 0 0 1 1 0 1 1 1 1 a s a4 s a5 s a6 s a7 s a8 c 4 0 0 1 1 0 1 1 0 1 a s a4 s a5 s a6 s a7 s a8 c 1 0 0 1 1 0 1 1 1 1 a s a4 s a5 s a6 s a7 s a8 c 2 0 0 1 1 0 1 1 1 1 a s a4 s a5 s a6 s a7 s a8 c 3 0 0 1 1 0 1 1 e 1 a s a4 s a5 s a6 s a7 s a8 c 4 0 0 1 1 0 1 1 e 1 a s a4 s a5 s a6 s a7 s a8 time slot 1 time slot 1 time slot 1 time slot 1 time slot 1 time slot 1 time slot 1 time slot 1 time slot 1 time slot 1 time slot 1 time slot 1 time slot 1 time slot 1 time slot 1 time slot 1 time slot 31 time slot 31 time slot 31 time slot 31 time slot 31 time slot 31 time slot 31 time slot 31 time slot 31 time slot 31 time slot 31 time slot 31 time slot 31 time slot 31 time slot 31 time slot 31 frame 0 of crc-4 multiframe time slot 0 time slot 1 time slot 16 time slot 31 si 1 a s a4 s a5 s a6 s a7 s a8 time slot 1 time slot 31 si 0 0 1 1 0 1 1 time slot 1 time slot 31 frame 15 of crc-4 multiframe fas frame not fas frame 0 0 0 0 x 0 y m x 1 x 2 12345678 8-bit time slot = 3.90625 m s 256-bit frame = 125 m s primary basic frame structure a 1 b 1 c 1 d 1 a 16 b 16 c 16 d 16 a 2 b 2 c 2 d 2 a 17 b 17 c 17 d 17 a 3 b 3 c 3 d 3 a 18 b 18 c 18 d 18 a 4 b 4 c 4 d 4 a 19 b 19 c 19 d 19 a 5 b 5 c 5 d 5 a 20 b 20 c 20 d 20 a 6 b 6 c 6 d 6 a 21 b 21 c 21 d 21 a 7 b 7 c 7 d 7 a 22 b 22 c 22 d 22 a 8 b 8 c 8 d 8 a 23 b 23 c 23 d 23 a 9 b 9 c 9 d 9 a 24 b 24 c 24 d 24 a 10 b 10 c 10 d 10 a 25 b 25 c 25 d 25 a 11 b 11 c 11 d 11 a 26 b 26 c 26 d 26 a 12 b 12 c 12 d 12 a 27 b 27 c 27 d 27 a 13 b 13 c 13 d 13 a 28 b 28 c 28 d 28 a 14 b 14 c 14 d 14 a 29 b 29 c 29 d 29 a 15 b 15 c 15 d 15 a 30 b 30 c 30 d 30 frame 0 time channel associated signaling multiframe in time slot 16 channel numbers refer to telephone channel numbers. time slots 1 to 15 and 17 to 31 are assigned to telephone channels numbered from 1 to 30. frame 15 crc-4 multiframe in time slot 0 time slot 16 multiframe slot 16 multiframe preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 46 lucent technologies inc. lucent technologies inc. frame formats (continued) cept 2.048 basic frame structure the itu rec. g.704 section 2.3.1 defined frame length is 256 bits, numbered 1 to 256. the frame repetition rate is 8 khz. the allocation of bits numbered 1 to 8 of the frame is shown in table 19. table 19. allocation of bits 1 to 8 of the fas frame and the not fas frame the function of each bit in table 19 is described below: n the si bits are reserved for international use. a specific use for these bits is described in table 20. itu crc-4 multiframe structure. if no use is realized, these bits should be fixed at 1 on digital paths crossing an interna- tional border. n bit 2 of the not fas frames is fixed to 1 to assist in avoiding simulations of the frame alignment signal. n bit 3 of the not fas is the remote alarm indication (a bit). in undisturbed operation, this bit is set to 0; in alarm condition, set to 1. n bits 48 of the not fas (sa4sa8) may be recommended by itu for use in specific point-to-point applica- tions. bit sa4 may be used as a message-based data link for operations, maintenance, and performance moni- toring. if the data link is accessed at intermediate points with consequent alterations to the sa4 bit, the crc-4 bits must be updated to retain the correct end-to-end path termination functions associated with the crc-4 pro- cedure. the receive framer does not implement the crc-4 modifying algorithm described in itu rec. g.706 annex c. bits sa4sa8, where these are not used, should be set to 1 on links crossing an international border. n msb = most significant bit and is transmitted first. n lsb = least significant bit and is transmitted last. basic frames bit 1 (msb) bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 (lsb) frame alignment signal (fas) si 0 0 1 1 0 1 1 not frame alignment signal (not fas) si 1 a sa4 sa5 sa6 sa7 sa8 lucent technologies inc. 47 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. frame formats (continued) transparent framing format the transmit framer can be programmed to transparently transmit 256 bits of system data to the line. the transmit framer must be programmed to either transparent framing mode 1 or transparent framing mode 2 (see table 136. framer reset and transparent mode control register (frm_pr26) (y7a)). in transparent mode 1 or mode 2, the transmit framer transmits all 256 bits of the rchi payload unmodified to the line. time slot 1 of the rchi, determined by the chifs signal, is inserted into the fas/not fas time slot of the transmit line interface. frame integrity is maintained in both the transmit and receive framer sections. 5-5988(f) figure 12. cept transparent frame structure in transparent framing mode 1, the receive framer is forced not to reframe on the receive line data. other than bipolar violations and unframed ais monitoring, there is no processing of the receive line data. the entire receive line payload is transmitted unmodified to the chi. in transparent framing mode 2, the receive framer functions normally on the receive line data. all normal monitoring of receive line data is performed and data is transmitted to the chi as programmed. time slot 1 32 time-slot chi frame time slot 2 time slot 3 time slot 31 time slot 32 time slot 1 32 time-slot line frame time slot 2 time slot 3 time slot 31 time slot 32 preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 48 lucent technologies inc. lucent technologies inc. frame formats (continued) cept loss of basic frame alignment (lfa) frame alignment is assumed to be lost when the follow- ing occurs : n as described in itu rec. g.706 section 4.1.1, three consecutive incorrect frame alignment signals have been received. n so as to limit the effect of spurious frame alignment signals, when bit 2 in time slot 0 in not fas frames has been received with an error on three consecutive occasions. n optionally, as described in itu rec. g.706 section 4.3.2, by exceeding a count of >914 errored crc-4 blocks out of 1000, with the understanding that a count of 3 915 errored crc blocks indicates false frame alignment. n on demand via the control registers. n in the lfa state: n no additional fas or not fas errors are processed. n the received remote frame alarm (received a bit) is deactivated. n all not fas bit (si bit, a bit, and sa4 to sa8 bits) processing is halted. n receive sa6 status bits are set to 0. n receive sa6 code monitoring and counting is halted. n all receive sa stack data updates are halted. the receive sa stack ready, register frm_sr4 bit 6 and bit 7, is set to 0. if enabled, the receive sa stack interrupt bit is set to 0. n receive data link (rfdl) is set to 1 and rfdclk maintains previous alignment. n optionally, the remote alarm indication (a = 1) may be automatically transmitted to the line if register frm_pr27 bit 0 is set to 1. n optionally, the alarm indication signal (ais) may be automatically transmitted to the system if register frm_pr19 bit 0 is set to 1. n if crc-4 is enabled, loss of crc-4 multiframe align- ment is forced. n if crc-4 is enabled, the monitoring and processing of crc-4 checksum errors is halted. n if crc-4 is enabled, all monitoring and processing of received e-bit information is halted. n if crc-4 is enabled, the receive continuous e-bit alarm is deactivated. n if crc-4 is enabled, optionally, e bit = 0 is transmit- ted to the line for the duration of loss of crc-4 multi- frame alignment if register frm_pr28 bit 4 is set to 1. n if time slot 16 signaling is enabled, loss of the signal- ing multiframe alignment is forced. n if time slot 16 signaling is enabled, updating of the signaling data is halted. cept loss of frame alignment recovery algorithm the receive framer begins the search for basic frame alignment one bit position beyond the position where the lfa state was detected. as defined in itu rec. g.706.4.1.2, frame alignment will be assumed to have been recovered when the following sequence is detected as follows: n for the first time, the presence of the correct frame alignment signal in frame n . n the absence of the frame alignment signal in the fol- lowing frame detected by verifying that bit 2 of the basic frame is a 1 in frame n + 1. n for the second time, the presence of the correct frame alignment in the next frame, n + 2. failure to meet the second or third bullet above will ini tiate a new basic frame search in frame n + 2. lucent technologies inc. 49 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. frame formats (continued) cept time slot 0 crc-4 multiframe structure the crc-4 multiframe is in bit 1 of each not fas frame. as described in itu rec. g.704 section 2.3.3.1, where there is a need to provide additional protection against simulation of the frame alignment signal, and/or where there is a need for an enhanced error monitoring capability, then bit 1 of each frame may be used for a cyclic redundancy check-4 (crc-4) procedure as detailed below. the allocation of bits 18 of time slot 0 of every frame is shown in table 20 for the complete crc-4 multiframe. table 20. itu crc-4 multiframe structure notes: c1 to c4 = cyclic redundancy check-4 (crc-4) bits. e = crc-4 error indication bits. sa4 to sa8 = spare bits. a = remote frame alarm (rfa) bit (active-high); referred to as the a bit. the crc-4 multiframe consists of 16 frames numbered 0 to 15 and is divided into two eight-frame submultiframes (smf), designated smf-i and smf-ii that signifies their respective order of occurrence within the crc-4 multi- frame structure. the smf is the crc-4 block size (2048 bits). in those frames containing the frame alignment sig- nal (fas), bit 1 is used to transmit the crc-4 bits. there are four crc-4 bits, designated c1, c2, c3, and c4 in each smf. in those frames not containing the frame alignment signal (not fas), bit 1 is used to transmit the 6-bit crc-4 multiframe alignment signal and two crc-4 error indication bits (e). the multiframe alignment signal is defined in itu rec. g.704 section 2.3.3.4, as 001011. transmitted e bits should be set to 0 until both basic frame and crc-4 multiframe alignment are established. thereafter, the e bits should be used to indicate received errored submultiframes by setting the binary state of one e bit from 1 to 0 for each errored submultiframe. the received e bits will always be taken into account, by the receive e-bit processor * , even when the smf that contains them is found to be errored. in the case where there exists equipment that does not use the e bits, the state of the e bits should be set to a binary 1 state. * the receive e-bit processor will halt the monitoring of the received e bit during the loss of crc-4 multiframe alignment. multiframe submultiframe (smf) frame number bits 12345678 i0c10011011 1 0 1 a sa4 sa5 sa6 sa7 sa8 2 c20011011 3 0 1 a sa4 sa5 sa6 sa7 sa8 4 c30011011 5 1 1 a sa4 sa5 sa6 sa7 sa8 6 c40011011 7 0 1 a sa4 sa5 sa6 sa7 sa8 ii 8 c10011011 9 1 1 a sa4 sa5 sa6 sa7 sa8 10 c2 0 0 1 1 0 1 1 11 1 1 a sa4 sa5 sa6 sa7 sa8 12 c3 0 0 1 1 0 1 1 13 e 1 a sa4 sa5 sa6 sa7 sa8 14 c4 0 0 1 1 0 1 1 15 e 1 a sa4 sa5 sa6 sa7 sa8 preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 50 lucent technologies inc. lucent technologies inc. frame formats (continued) the crc-4 word, located in submultiframe n, is the remainder after multiplication by x 4 and then division (modulo 2) by the generator polynomial x 4 + x + 1, of the polynomial representation of the submultiframe n C 1. representing the contents of the submultiframe check block as a polynomial, the first bit in the block, i.e., frame 0, bit 1 or frame 8, bit 1, is taken as being the most significant bit and the least significant bit in the check block is frame 7 or frame 15, bit 256. similarly, c 1 is defined to be the most significant bit of the remainder and c 4 the least significant bit of the remain- der. the encoding procedure, as described in itu rec. g.704 section 2.3.3.5.2, follows: n the crc-4 bits in the smf are replaced by binary 0s. n the smf is then acted upon the multiplication/divi- sion process referred to above. n the remainder resulting from the multiplication/divi- sion process is stored, ready for insertion into the respective crc-4 locations of the next smf. the decoding procedure, as described in itu rec. g.704 section 2.3.3.5.3, follows: n a received smf is acted upon by the multiplication/ division process referred to above, after having its crc-4 bits extracted and replaced by 0s. n the remainder resulting from this division process is then stored and subsequently compared on a bit-by- bit basis with the crc bits received in the next smf. n if the remainder calculated in the decoder exactly corresponds to the crc-4 bits received in the next smf, it is assumed that the checked smf is error- free. cept loss of crc-4 multiframe alignment (lts0mfa) loss of basic frame alignment forces the receive framer into a loss of crc-4 multiframe alignment state. this state is reported by way of the status registers frm_sr1 bit 2. once basic frame alignment is achieved, a new search for crc-4 multiframe align- ment is initiated. during a loss of crc-4 multiframe alignment state the following occurs: n the crc-4 error counter is halted. n the crc-4 error monitoring circuit for errored sec- onds and severely errored seconds is halted. n the received e-bit counter is halted. n the received e-bit monitoring circuit for errored sec- onds and severely errored seconds at the remote end interface is halted. n receive continuous e-bit monitoring is halted. n all receive sa6 code monitoring and counting func- tions are halted. n the updating of the receive sa stack is halted and the receive sa stack interrupt is deactivated. n optionally, a = 1 may be automatically transmitted to the line if register frm_pr27 bit 2 is set to 1. n optionally, e = 0 may be automatically transmitted to the line if register frm_pr28 bit 4 is set to 1. n optionally, if lts0mfa monitoring in the perfor- mance counters is enabled, by setting registers frm_pr14 through frm_pr17 bit 1 to 1, then these counts are incremented once per second for the duration of the lts0mfa state. lucent technologies inc. 51 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. frame formats (continued) cept loss of crc-4 multiframe alignment recovery algorithms several optional algorithms exist in the receive framer. these are selected through programming of register frm_pr9. crc-4 multiframe alignment algorithm with 8 ms timer the default algorithm is as described in itu rec. g.706 section 4.2. the recommendation states that if a condition of assumed frame alignment has been achieved, crc-4 multiframe alignment is deemed to have occurred if at least two valid crc-4 multiframe alignment signals can be located within 8 ms, the time separating two crc-4 multiframe signals being 2 ms or a multiple of 2 ms. the search for the crc-4 multi- frame alignment signal is made only in bit 1 of not fas frames. if multiframe alignment cannot be achieved within 8 ms, it is assumed that frame align- ment is due to a spurious frame alignment signal and a new parallel search for basic frame alignment is initi- ated. the new search for the basic frame alignment is started at the point just after the location of the assumed spurious frame alignment signal. during this parallel search for basic frame alignment, there is no indication to the system of a receive loss of frame align- ment (rlfa) state. during the parallel search for basic frame alignment and while in primary basic frame align- ment, data will flow through the receive framer to the system interface as defined by the current primary frame alignment. the receive framer will continuously search for crc-4 multiframe alignment. crc-4 multiframe alignment algorithm with 100 ms timer the crc-4 multiframe alignment with 100 ms timer mode is enabled by setting frm_pr9 to 0xxxx1x1 (binary). this crc-4 multiframe reframe mode starts a 100 ms timer upon detection of basic frame alignment. this is a parallel timer to the 8 ms timer. if crc-4 multi- frame alignment cannot be achieved within the time limit of 100 ms due to the crc-4 procedure not being implemented at the transmitting side, then an indication is given, and actions are taken equivalent to those specified for loss of basic frame alignment, namely: n optional automatic transmission of a = 1 to the line if register frm_pr27 bit 3 is set to 1. n optional automatic transmission of e = 0 to the line if register frm_pr28 bit 5 is set to 1. n optional automatic transmission of ais to the system if register frm_pr19 bit 1 is set to 1. preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 52 lucent technologies inc. lucent technologies inc. frame formats (continued) 5-3909(f).er.2 figure 13. receive crc-4 multiframe search algorithm using the 100 ms internal timer ? set e bits according to itu rec. g.704, section 2.3.3.4 out of primary bfa: ? optionally disable traffic by transmitting ais to the system ? optionally transmit a = 1 and e = 0 to line ? inhibit incoming crc-4 performance monitoring bfa search? in primary bfa: ? enable traffic to the system ? transmit a = 0 and optionally e = 0 to the line ? start 8 ms and 100 ms timers ? enable primary bfa loss checking process crc-4 mfa search (itu rec. g.706, section 4.2 - note 2 ) can crc-4 mfa be found in 8 ms? parallel bfa search 100 ms timer elapsed? yes no no no yes yes assume crc-4 multiframe alignment: ? confirm primary bfa associated with crc-4 mfa ? adjust primary bfa if necessary set 100 ms timer expiration status bit to the 1 state: ? optionally transmit a bit = 1 to the line interface for the duration of lts0mfa = 1 ? optionally transmit ais to the system interface for the start crc-4 performance monitoring: ? set e bits according to itu rec. g.704, section 2.3.3.4 crc-4 count > 914 in 1 second or continue crc-4 performance monitoring: yes yes no no duration of lts0mfa = 1 is 100 ms trx = 1 ? yes no set internal 100 ms timer expiration status bit to 0: ? if transmitting a bit = 1 to the line interface, transmit a bit = 0 ? if transmitting ais to the system interface, enable data transmission to the system interface lfa = 1? good? is ? yes no 100 ms trx = 1 internal set internal 100 ms timer expiration status bit to 1: primary ? if transmitting e = 0 to the line interface, transmit e bit = 1 ? optionally transmit e bit = 0 to the line interface for the duration of ltsomfa = 1 lucent technologies inc. 53 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. frame formats (continued) crc-4 multiframe alignment search algorithm with 400 ms timer the crc-4 multiframe alignment with 400 ms timer mode is enabled by setting frm_pr9 to 0xxx1xx1 (binary). this receive crc-4 multiframe reframe mode is the modified crc-4 multiframe alignment algorithm described in itu rec. 706 annex b, where it is referred to as crc-4-to-non-crc-4 equipment interworking. a flow diagram of this algorithm is illustrated in figure 14. when the interworking algorithm is enabled, it supersedes the 100 ms algorithm described on page 51 and in figure 13. this algorithm assumes that a valid basic frame alignment signal is consistently present, but the crc-4 multiframe alignment cannot be achieved by the end of the total crc-4 multiframe alignment search period of 400 ms, if the distant end is a non-crc-4 equipment. in this mode, the following consequent actions are taken: n an indication that there is no incoming crc-4 multi- frame alignment signal. n all crc-4 processing on the receive 2.048 mbits/s signal is inhibited. n crc-4 data is transmitted to the distant end with both e bits set to 0. this algorithm allows the identification of failure of crc-4 multiframe alignment generation/detection, but with correct basic framing, when interworking between each piece of equipment having the modified crc-4 multiframe alignment algorithm. as described in itu rec. g.706 section b.2.3: n a 400 ms timer is triggered on the initial recovery of the primary basic frame alignment. n the 400 ms timer reset if and only if: the criteria for loss of basic frame alignment as described in itu rec. g.706 section 4.1.1 is achieved. if 915 out of 1000 errored crc-4 blocks are detected resulting in a loss of basic frame align- ment as described in itu rec. g.706 section 4.3.2. on-demand reframe is requested. the receive framer is programmed to the non- crc-4 mode. n the loss of basic frame alignment checking process runs continuously, irrespective of the state of the crc-4 multiframe alignment process below it. n a new search for frame alignment is initiated if crc-4 multiframe alignment cannot be achieved in 8 ms, as described in itu rec. g.706 section 4.2. this new search for basic frame alignment will not reset the 400 ms timer or invoke consequent actions associated with loss of the primary basic frame align- ment. in particular, all searches for basic frame align- ment are carried out in parallel with, and independent of, the primary basic frame loss check- ing process. all subsequent searches for crc-4 mul- tiframe alignment are associated with each basic framing sequence found during the parallel search. n during the search for crc-4 multiframe alignment, traffic is allowed through, upon, and to be synchro- nized to, the initially determined primary basic frame alignment. n upon detection of the crc-4 multiframe before the 400 ms timer elapsing, the basic frame alignment associated with the crc-4 multiframe alignment replaces, if necessary, the initially determined basic frame alignment. n if crc-4 multiframe alignment is not found before the 400 ms timer elapses, it is assumed that a condi- tion of interworking between equipment with and without crc-4 capability exists and the actions described above are taken. n if the 2.048 mbits/s path is reconfigured at any time, then it is assumed that the (new) pair of path termi- nating equipment will need to re-establish the com- plete framing process, and the algorithm is reset. preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 54 lucent technologies inc. lucent technologies inc. frame formats (continued) 5-3909(f).fr.3 figure 14. receive crc-4 multiframe search algorithm for automatic, crc-4/non-crc-4 equipment interworking as defined by itu (from itu rec. g.706, annex b.2.2 - 1991) ? set e bits according to itu rec. g.704, section 2.3.3.4 out of primary bfa: ? optionally disable traffic by transmitting ais to the system ? optionally transmit a bit = 1 and e bit = 0 to line ? inhibit incoming crc-4 performance monitoring bfa search? in primary bfa: ? enable traffic not transmitting ais to the system ? transmit a = 0 and optionally e = 0 to the line ? start 400 ms timer ? enable primary bfa loss checking process crc-4 mfa search (itu rec. g.706, section 4.2) can crc-4 mfa be found in 8 ms? parallel bfa search 400 ms timer elapsed? yes no no no yes yes assume crc-4-to-crc-4 interworking: ? confirm primary bfa associated with crc-4 mfa ? adjust primary bfa if necessary start crc-4 performance monitoring: ? set e bits according to itu rec. g.704, section 2.3.3.4 crc-4 count > 914 in 1 second or continue crc-4 performance monitoring: yes yes no no ? ? keep a = 0 in outgoing crc-4 data assume crc-4-to-non-crc-4 interworking: ? transmit a bit = 0 to the line interface ? stop incoming crc-4 processing ? confirm primary bfa ? transmit e bit = 0 to the line interface ? indicate no crc-4 mfa primary lfa = 1? lucent technologies inc. 55 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. frame formats (continued) cept time slot 16 multiframe structure the TFRA08C13 supports two cept signaling modes: channel associated signaling (cas) or per-channel signal- ing (pcs0 and pcs1). channel associated signaling (cas) the channel associated signaling (cas) mode utilizes time slot 16 of the fas and not fas frames. the cas for- mat is a multiframe consisting of 16 frames where frame 0 of the multiframe contains the multiframe alignment pat- tern of four zeros in bits 1 through 4. table 21 illustrates the cas multiframe of time slot 16. the TFRA08C13 can be programmed to force the transmitted line cas multiframe alignment pattern to be transmitted in the fas frame by selecting the pcs0 option or in the not fas frame by selecting the pcs1 option. alignment of the transmitted line cas multiframe to the crc-4 multiframe is arbitrary. table 21. itu cept time slot 16 channel associated signaling multiframe structure notes: frame 0 bits 14 define the time slot 16 multiframe alignment. x0x2 = time slot 16 spare bits defined in frm_pr41 bit 0bit 2. y m = yellow alarm, time slot 16 remote multiframe alarm (rma) bit (1 = alarm condition). time slot 16 channel associated signaling multiframe frame number bit 123 4 5 6 7 8 0 000 0 x 0 y m x 1 x 2 1a 1 b 1 c 1 d 1 a 16 b 16 c 16 d 16 2a 2 b 2 c 2 d 2 a 17 b 17 c 17 d 17 3a 3 b 3 c 3 d 3 a 18 b 18 c 18 d 18 4a 4 b 4 c 4 d 4 a 19 b 19 c 19 d 19 5a 5 b 5 c 5 d 5 a 20 b 20 c 20 d 20 6a 6 b 6 c 6 d 6 a 21 b 21 c 21 d 21 7a 7 b 7 c 7 d 7 a 22 b 22 c 22 d 22 8a 8 b 8 c 8 d 8 a 23 b 23 c 23 d 23 9a 9 b 9 c 9 d 9 a 24 b 24 c 24 d 24 10 a 10 b 10 c 10 d 10 a 25 b 25 c 25 d 25 11 a 11 b 11 c 11 d 11 a 26 b 26 c 26 d 26 12 a 12 b 12 c 12 d 12 a 27 b 27 c 27 d 27 13 a 13 b 13 c 13 d 13 a 28 b 28 c 28 d 28 14 a 14 b 14 c 14 d 14 a 29 b 29 c 29 d 29 15 a 15 b 15 c 15 d 15 a 30 b 30 c 30 d 30 preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 56 lucent technologies inc. lucent technologies inc. frame formats (continued) cept loss of time slot 16 multiframe align- ment (lts16mfa) loss of basic frame alignment forces the receive framer into a loss of time slot 16 signaling multiframe align- ment state. in addition, as defined in itu rec. g.732 section 5.2, time slot 16 signaling multiframe is assumed lost when two consecutive time slot 16 multi- frame 4-bit all-zero patterns is received with an error. in addition, the time slot 16 multiframe is assumed lost when, for a period of two multiframes, all bits in time slot 16 are in state 0. this state is reported by way of the status registers frm_sr1 bit 1. once basic frame alignment is achieved, the receive framer will initiate a search for the time slot 16 multiframe alignment. during a loss of time slot 16 multiframe alignment state, the following occurs: n the updating of the signaling data is halted. n the received control bits forced to the binary 1 state. n the received remote multiframe alarm indication sta- tus bit is forced to the binary 0 state. n optionally, the transmit framer can transmit to the line the time slot 16 signaling remote multiframe alarm if register frm_pr41 bit 4 is set to 1. n optionally, the transmit framer can transmit the alarm indication signal (ais) in the system transmit time slot 16 data if register frm_pr44 bit 6 is set to 1. cept loss of time slot 16 multiframe align- ment recovery algorithm the time slot 16 multiframe alignment recovery algo- rithm is as described in itu rec. g.732 section 5.2. the recommendation states that if a condition of assumed frame alignment has been achieved, time slot 16 multiframe alignment is deemed to have occurred when the 4-bit time slot 16 multiframe pattern of 0000 is found in time slot 16 for the first time, and the preced- ing time slot 16 contained at least one bit in the binary 1 state. cept time slot 0 fas/not fas control bits fas/not fas si- and e-bit source the si bit can be used as an 8 kbits/s data link to and from the remote end, or in the crc-4 mode, it can be used to provide added protection against false frame alignment. the sources for the si bits that are transmit- ted to the line are the following: n cept with no crc-4 and frm_pr28 bit 0 = 1: the tsif control bit (frm_pr28 bit 1) is transmitted in bit 1 of all fas frames and the tsinf control bit (frm_pr28 bit 2) is transmitted in bit 1 of all not fas frames. n the chi system interface (cept with no crc-4 and frm_pr28 bit 0 = 0) * . n this option requires the received system data (rchi- data) to maintain a biframe alignment pattern where frames containing si bit information for the not fas frames have bit 2 of time slot 0 in the binary 1 state followed by frames containing si bit information for the fas frames that have bit 2 of time slot 0 in the binary 0 state. this ensures the proper alignment of the si received system data to the transmit line si data. whenever this requirement is not met by the system, the transmit framer will enter a loss of biframe alignment condition (indication is given in the status registers) and then search for the pattern; in the loss of biframe alignment state, transmitted line data is corrupted (only when the system interface is sourcing sa or si data). when the transmit framer locates a new biframe alignment pattern, an indica- tion is given in the status registers and the transmit framer resumes normal operations. * whenever bits (e.g., si, sa, etc.) are transmitted from the system transparently, frm_pr29 must first be momentarily written to 001xxxxx (binary). otherwise, the transmit framer will not be able to locate the biframe alignment. lucent technologies inc. 57 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. cept time slot 0 fas/not fas control bits (continued) n cept with crc-4 1 : manual transmission of e bit = 0: if frm_pr28 bit 0 = 0, then the tsif bit (frm_pr28 bit 1) is transmitted in bit 1 of frame 13 (e bit) and the tsinf bit (frm_pr28 bit 2) is transmitted in bit 1 of frame 15 (e bit). if frm_pr28 bit 0 = 1, then each time 0 is written into tsif (frm_pr28 bit 1) one e bit = 0 is trans- mitted in frame 13, and each time 0 is written into tsinf (frm_pr28 bit 2) one e bit = 0 is transmit- ted in frame 15. n cept with crc-4 1 , automatic transmission of e bit = 0: optionally, one transmitted e bit is set to 0 by the transmit framer, as described in itu rec. g.704 section 2.3.3.4, for each received errored crc-4 submultiframe detected by the receive framer if frm_pr28 bit 3 = 1. optionally, as described in itu rec. g.704 sec- tion 2.3.3.4, both e bits are set to 0 while in a received loss of crc-4 multiframe alignment state 2 if frm_pr28 bit 4 = 1. optionally, when the 100 ms or 400 ms timer is enabled and the timer has expired, as described in itu rec. g.706 section b.2.2, both e bits are set to 0 for the duration of the loss of crc-4 multi- frame alignment state 2 if frm_pr28 bit 5 = 1. otherwise, the e bits are transmitted to the line in the 1 state. not fas a-bit (cept remote frame alarm) sources the a bit, as described in itu rec. g.704 section 2.3.2, table 4a/g.704, is the remote alarm indication bit. in undisturbed conditions, this bit is set to 0 and transmitted to the line. in the loss of frame alignment (lfa) state, this bit may be set to 1 and transmitted to the line as determined by register frm_pr27. the a bit is set to 1 and transmitted to the line for the following conditions: n setting the transmit a bit = 1 control bit by setting register frm_pr27 bit 7 to 1. n optionally for the following alarm conditions as selected through programming register frm_pr27. the duration of loss of basic frame alignment as described in itu rec. g.706 section 4.1.1 3 , or itu rec. g.706 section 4.3.2 4 if register frm_pr27 bit 0 = 1. the duration of loss of crc-4 multiframe align- ment if register frm_pr27 bit 2 = 1. the duration of loss of signaling time slot 16 multi- frame alignment if register frm_pr27 bit 1 = 1. the duration of loss of crc-4 multiframe align- ment after either the 100 ms or 400 ms timer expires if register frm_pr27 bit 3 = 1. the duration of receive sa6_8hex 5 if register frm_pr27 bit 4 = 1. the duration of receive sa6_chex 5 if register frm_pr27 bit 5 = 1. not fas sa-bit sources 6 the sa bits, sa4sa8, in the not fas frame can be a 4 kbits/s data link to and from the remote end. the sources and value for the sa bits are as follows: n the sa source register frm_pr29 bit 0bit 4 if frm_pr29 bit 7bit 5 = 000 (binary) and frm_pr30 bit 4bit 0 = 11111 (binary). n the facility data link external input (tfdl) if register frm_pr29 bit 7 = 1 and register frm_pr21 bit 6 = 1. n the internal fdl-hdlc if register frm_pr29 bit 7 = 1 and register frm_pr21 bit 6 = 0. n the sa transmit stack if register frm_pr29 bit 7bit 5 are set to 01x (binary). 1. the receive e-bit processor will halt the monitoring of received e bits during loss of crc-4 multiframe alignment. 2. whenever loss of frame alignment occurs, then loss of crc-4 multiframe alignment is forced. once frame alignment is estab- lished, then and only then, is the search for crc-4 multiframe alignment initiated. the receive framer unit, when programmed for crc-4, can be in a state of lfa and lts0mfa or in a state of lts0mfa only, but cannot be in a state of lfa only. 3. lfa is due to framing bit errors. 4. lfa is due to detecting 915 out of 1000 received crc-4 errored blocks. 5. see table 29 . sa6 bit coding recognized by the receive framer, for a definition of this sa6 pattern. 6. whenever bits (e.g., si, sa, etc.) are transmitted from the system transparently, frm_pr29 must first be momentarily written to 001xxxxx (binary). otherwise, the transmit framer will not be able to locate the biframe alignment. 58 58 lucent technologies inc. preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 lucent technologies inc. cept time slot 0 fas/not fas control bits (continued) n the chi system interface if register frm_pr29 bit 7bit 5 are set to 001 (binary). this option requires the received system data (rchidata) to maintain a biframe alignment pattern where (1) frames contain- ing sa bit information have bit 2 of time slot 0 in the binary 1 state and (2) these not fas frames are fol- lowed by frames not containing sa bit information, the fas frames, which have bit 2 of time slot 0 in the binary 0 state. this ensures the proper alignment of the sa received system data to the transmit line sa data. whenever this requirement is not met by the system, the transmit framer will enter a loss of biframe alignment condition indicated in the status register, frm_sr1 bit 4, and then search for the pat- tern. in the loss of biframe alignment state, transmit- ted line data is corrupted (only when the system interface is sourcing sa or si data). when the trans- mit framer locates a new biframe alignment pattern, an indication is given in the status registers and the transmit framer resumes normal operations. the receive sa data is present at the following: n the sa received stack, registers frm_sr54 frm_sr63, if the TFRA08C13 is programmed in the sa stack mode. n the system transmit interface. the status of the received sa bits and the received sa stack is available in status register frm_sr4. the transmit and receive sa bit for the fdl can be selected by setting register frm_pr43 bit 0bit 2 as shown in table 148. sa facility data link access the data link interface may be used to source one of the sa bits. access is controlled by registers frm_pr29, frm_pr30, and frm_pr43, see not fas sa-bit sources on page 57. the receive sa data is always present at the receive facility data link output pin, rfdl, along with a valid clock signal at the receive facility clock output pin, rfdlck. during a loss of frame alignment (lfa) state, the rfdl signal is forced to a 1 state while rfdlck continues to toggle on the previous frame alignment. when basic frame alignment is found, rfdl is as received from the selected receive sa bit position and rfdlck is forced (if necessary) to the new alignment. the data rate for this access mode is 4 khz. the access timing for the transmit and receive facility data is illustrated in figure 15 below. during loss of receive clock (lofrmrlck), rfdl and rfdlck are frozen in a state at the point of the lofrmrlck being asserted. 5-3910(f).dr.1 figure 15. facility data link access timing of the transmit and receive framer sections in the cept mode t8 t9 t9 t10 t11 t8: tfdlck cycle = 250 m s t9: tfdl to tfdlck setup/hold = 40 ns t10: rfdlck cycle = 250 m s t11: rfdlck to rfdl delay = 40 ns tfdlck tfdl rfdlck rfdl lucent technologies inc. 59 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. cept time slot 0 fas/not fas control bits (continued) not fas sa stack source and destination the transmit sa4 to sa8 bits may be sourced from the transmit sa stack, registers frm_pr31frm_pr40. the sa stack consists of ten 8-bit registers that contain 16 not fas frames of sa information as shown in table 22. the transmit stack data may be transmitted either in non-crc-4 mode or in crc-4 mode to the line. the receive stack data, registers frm_sr54frm_sr63, is valid in both the non-crc-4 mode and the crc-4 mode. in the non-crc-4 mode while in the loss of frame alignment (lfa) state, updating of the receive sa stack is halted and the transmit and receive stack interrupts are deactivated. in the crc-4 mode while in the loss of time slot 0 multiframe alignment (lts0mfa) state, updating of the receive sa stack is halted and the transmit and receive stack interrupts are deactivated. table 22. transmit and receive sa stack structure the most significant bit of the first byte is transmitted to the line in frame 1 of a double crc-4 multiframe. the least significant bit of the second byte is transmitted to the line in frame 31 of the double crc-4 multiframe. the protocol for accessing the sa stack information for the transmit and receive sa4 to sa8 bits is shown in figure 16 and described briefly below. the device indicates that it is ready for an update of its transmit stack by setting register frm_sr4 bit 7 (cept transmit sa stack ready) high. at this time, the system has about 4 ms to update the stack. data written to the stack during this interval will be transmitted during the next double crc-4 multiframe. by reading register frm_sr4 bit 7, the system clears this bit so that it can indicate the next time the transmit stack is ready. if the transmit stack is not updated, then the content of the stack is retransmitted to the line. the 32-frame interval of the transmit framer in the non-crc-4 mode is arbitrary. enabling transmit crc-4 mode forces the updating of the internal transmit stack at the end of the 32-frame crc-4 double multiframe; the transmit sa stack is then transmitted synchronous to the transmit crc-4 multiframe structure. on the receive side, the TFRA08C13 indicates that it has received data in the receive sa stack, register frm_sr54frm_sr63, by setting register frm_sr4 bit 6 (cept receive sa stack ready) high. the system then has about 4 ms to read the contents of the stack before it is updated again (old data lost). by reading register frm_sr4 bit 6, the system clears this bit so that it can indicate the next time the receive stack is ready. the receive framer always updates the content of the receive stack so unread data will be overwritten. the last 16 valid sa4 to sa8 bits are always stored in the receive sa stack on a double-multiframe boundary. the 32-frame interval of the receive framer in the non-crc-4 mode is arbitrary. enabling the receive crc-4 mode forces updating of the receive sa stack at the end of the 32-frame crc-4 double multiframe. the receive sa stack is received synchro- nous to the crc-4 multiframe structure. register number bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 + bit 0 (lsb) 1 sa4-1 sa4-3 sa4-5 sa4-7 sa4-9 sa4-11 sa4-13 sa4-15 2 sa4-17 sa4-19 sa4-21 sa4-23 sa4-25 sa4-27 sa4-29 sa4-31 3 sa5-1 sa5-3 sa5-5 sa5-7 sa5-9 sa5-11 sa5-13 sa5-15 4 sa5-17 sa5-19 sa5-21 sa5-23 sa5-25 sa5-27 sa5-29 sa5-31 5 sa6-1 sa6-3 sa6-5 sa6-7 sa6-9 sa6-11 sa6-13 sa6-15 6 sa6-17 sa6-19 sa6-21 sa6-23 sa6-25 sa6-27 sa6-29 sa6-31 7 sa7-1 sa7-3 sa7-5 sa7-7 sa7-9 sa7-11 sa7-13 sa7-15 8 sa7-17 sa7-19 sa7-21 sa7-23 sa7-25 sa7-27 sa7-29 sa7-31 9 sa8-1 sa8-3 sa8-5 sa8-7 sa8-9 sa8-11 sa8-13 sa8-15 10 sa8-17 sa8-19 sa8-21 sa8-23 sa8-25 sa8-27 sa8-29 sa8-31 preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 60 lucent technologies inc. lucent technologies inc. cept time slot 0 fas/not fas control bits (continued) 5-3911(f).c figure 16. transmit and receive sa stack accessing protocol system access sa stack (sass) interval: transmit framer unit transmits to the line the data in the transmit sa stack written during the previous sass interval. the system can update the transmit sa stack registers for transmission in the next crc-4 double multiframe. the system can read the receive sa stack registers to access the sa bits extracted during the previous valid (in multiframe alignment) double crc-4 multiframe. start of crc-4 double multiframe: ? basic frame alignment found, or, ? crc-4 multiframe alignment found. 1) 2) 3) 31 frames system access sa stack interval crc-4 double multiframe start frame 1 of 32 in dmf. internal sa stack update interval 31 frames 1-frame interval crc-4 double multiframe: 32 frames system access is disabled during this interval: the internal transmit sa stack is updated from the framer units 10-byte transmit stack control registers during this 1-frame interval. access to the stack control registers is disabled during this 1-frame interval. 1) 2) once loaded, the information in the internal transmit sa stack is transmitted to the line during the next crc-4 double multiframe, aligned to the crc-4 multiframe. if the transmit sa stack is not updated, then the content of the transmit sa stacks is retransmitted to the line. the system read-only receive stack is updated from the internal receive stack information registers. in non-crc-4 mode, the receive sa stack extracting circuitry assumes an arbitrary double 16-frame multiframe structure (32 frames), and data is extracted only in the frame aligned state. in crc-4 mode, the receive sa stack information is aligned to a crc-4 double multiframe structure (32 frames), and the data is extracted only in crc-4 multiframe aligned state. 1 frame 3) 4) 5) 6) 7) (dmf): 32 frames lucent technologies inc. 61 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. cept time slot 0 fas/not fas control bits (continued) interrupts indicating that the transmit sa stack or the receive sa stack are ready for system access are avail- able, see register frm_sr4 bit 6 and bit 7. cept time slot 16 x0x2 control bits each of the three x bits in frame 0 of the time slot 16 multiframe can be used as a 0.5 kbits/s data link to and from the remote end. the transmitted line x bits are sourced from control register frm_pr41 bit 0bit 2. in the loss of ts16 multiframe alignment (lts16mfa) state, receive x bits are set to 1 in status register frm_sr53. signaling access signaling information can be accessed by three differ- ent methods: transparently through the chi, via the control registers, or via the chi associated signaling mode. transparent signaling this mode is enabled by setting register frm_pr44 bit 0 to 1. data at the received rchidata interface passes through the framer undisturbed. the framer generates an arbitrary signaling multiframe in the transmit and receive directions to facilitate the access of signaling information at the system interface. ds1: robbed-bit signaling microprocessor control registers to enable signaling, register frm_pr44 bit 0 must be set to 0 (default). the information written into the f and g bits of the transmit signaling registers, frm_tsr0 frm_tsr23, define the robbed-bit signaling mode for each channel for both the transmit and receive direc- tions. the per-channel programming allows the system to combine voice channels with data channels within the same frame. the receive-channel robbed-bit signaling mode is always defined by the state of the f and g bits in the corresponding transmit signaling registers for that channel. the received signaling data is stored in the receive signaling registers, frm_rsr0 frm_rsr23, while receive framer is in both the frame and superframe alignment states. updating the receive signaling registers can be inhibited on-demand, by set- ting register frm_pr44 bit 3 to 1, or automatically when either a framing error event, a loss of frame, or superframe alignment state is detected or a controlled slip event occurs. the signaling inhibit state is valid for at least 32 frames after any one of the following: a framing errored event, a loss of frame and/or super- frame alignment state, or a controlled slip event. in the common channel signaling mode, data written in the transmit signaling registers is transmitted in chan- nel 24 of the transmit line bit stream. the f and g bits are ignored in this mode. the received signaling data from channel 24 is stored in receive signaling registers frm_rsr0frm_rsr23 for t1. associated signaling mode this mode is enabled by setting register frm_pr44 bit 2 to 1. signaling information in the associated signaling mode (asm) is allocated an 8-bit system time slot in conjunc- tion with the payload data information for a particular channel. the default system data rate in the asm mode is 4.096 mbits/s. each system channel consists of an 8-bit payload time slot followed by its correspond- ing 8-bit signaling time slot. the format of the signaling byte is identical to that of the signaling registers. in the asm mode, writing the transmit signaling regis- ters will corrupt the transmit signaling data. in the trans- mit signaling register asm (tsr-asm) format, enabled by setting register frm_pr44 bit 2 and bit 5 to 1, the system must write into the f and g bit * of the transmit signaling registers to program the robbed-bit signaling state mode of each ds0. the abcd bits are sourced from the rchi ports when tsr-asm mode is enabled. * all other bits in the signaling registers are ignored, while the f and g bits in the received rchidata stream are ignored. preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 62 lucent technologies inc. lucent technologies inc. signaling access (continued) table 23 illustrates the asm time-slot format for valid channels. table 23. associated signaling mode chi 2-byte time-slot format for ds1 frames * x indicates bits that are undefined by the framer. ? the identical sense of the received system p bit in the transmitted signaling data is echoed back to the system in the receive d signaling information. the ds1 framing formats require rate adaptation from the line-interface 1.544 mbits/s bit stream to the system- interface 4.096 mbits/s bit stream. the rate adaptation results in the need for stuffed time slots on the system inter- face. table 24 illustrates the asm format for t1 stuffed channels used by the TFRA08C13. the stuffed data byte contains the programmable idle code in register frm_pr23 (default = 7f (hex)), while the signaling byte is ignored. table 24. associated signaling mode chi 2-byte time-slot format for stuffed channels * x indicates bits which are undefined by the framer. cept: time slot 16 signaling microprocessor control registers to enable signaling, register frm_pr44 bit 0 must be set to 0 (default). the information written into transmit signaling control registers frm_tsr0frm_tsr31 define the state of the abcd bits of time slot 16 transmitted to the line. the received signaling data from time slot 16 is stored in receive signaling registers frm_rsr0frm_rsr31. associated signaling mode signaling information in the associated signaling mode (asm), register frm_pr44 bit 2 = 1, is allocated an 8-bit system time slot in conjunction with the data information for a particular channel. the default system data rate in the asm mode is 4.096 mbits/s. each system channel consists of an 8-bit payload time slot followed by its associ- ated 8-bit signaling time slot. the format of the signaling byte is identical to the signaling registers. table 25 illustrates the asm time-slot format for valid cept e1 time slots table 25. associated signaling mode chi 2-byte time-slot format for cept * in the cept formats, these bits are undefined. ? the p bit is the parity-sense bit calculated over the 8 data bits, the abcd (and e) bits, and the p bit. the identical sense o f the received system p bit in the transmitted signaling data is echoed back to the system in the received signaling information. ds1: asm chi time slot payload data signaling information* 12345678abcdxfgp ? asm chi time slot payload data signaling information* 01111111 xxxxxxxx cept asm chi time slot payload data signaling information 12345678abcdex * x * p ? lucent technologies inc. 63 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. auxiliary framer i/o timing transmit and receive timing and data signals are provided by terminals rfrmck (receive framer clock), rfrm- data (receive framer data), rfs (receive frame sync), rssfs (receive framer signaling superframe sync), rcrc- mfs (receive frame crc-4 multiframe sync), tfs (transmit framer frame sync), tssfs (transmit framer signaling superframe sync), tcrcmfs (transmit framer crc-4 multiframe sync). the receive signals are synchronized to the recovered receive line clock, rlck, and the transmit signals are syn- chronized to the transmit line clock, tlck. note that tlck must be phase locked to the chi clock, chick, see table 2. pin descriptions, pin d18. detailed timing specifications for these signals are given in figure 17figure 24. 5-6290(f)r.6 figure 17. timing specification for rfrmck, rfrmdata, and rfs in ds1 mode 5-6292(f)r.7 figure 18. timing specification for tfs, tlck, and tpd in ds1 mode rfrmck rfs rfrmdata time slot 1 time slot 24 bit 7 bit 1 data valid bit 0 125 m s tlck tfs tpd ts1 125 m s ts1 (single rail) ts2 ts24 f bit bit 0 (msb) f bit bit 0 (msb) preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 64 lucent technologies inc. lucent technologies inc. auxiliary framer i/o timing (continued) 5-6294(f)r.6 figure 19. timing specification for rfrmck, rfrmdata, and rfs in cept mode 5-6295(f)r.8 figure 20. timing specification for rfrmck, rfrmdata, rfs, and rssfs in cept mode rfrmck rfs rfrmdata fas/nfas: time slot 0 time slot 31 bit 7 bit 1 data valid bit 0 125 m s rfrmck rfs rssfs rfrmdata ts0 of the frame after the frame containing the 2 ms signaling multiframe pattern (0000) ts0 of the frame after the frame containing the signaling multiframe pattern (0000) 125 m s lucent technologies inc. 65 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. auxiliary framer i/o timing (continued) 5-6296(f)r.5 figure 21. timing specification for rcrcmfs in cept mode 5-6297(f)r.5 figure 22. timing specification for tfs, tlck, and tpd in cept mode rfrmclk rfs rcrcmfs rfrmdata ts0 of frame #0 of multiframe ts0 of frame #0 of multiframe 2 ms tlck tfs tpd ts0 of frame x 125 m s ts0 of frame x + 1 (single rail) preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 66 lucent technologies inc. lucent technologies inc. auxiliary framer i/o timing (continued) 5-6298(f)r.5 figure 23. timing specification for tfs, tlck, tpd, and tssfs in cept mode 5-6299(f)r.5 figure 24. timing specification for tfs, tlck, tpd, and tcrcmfs in cept mode tfs tlck tssfs tpd (single ts0 of the frame 2 ms 11 clock cycles containing the signaling multiframe pattern (0000) rail) tlck tfs tcrcmfs tpd (single ts0 of frame #8 1 ms of multiframe rail) ts0 of frame #0 of multiframe ts0 of frame #0 of multiframe 1 ms lucent technologies inc. 67 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. alarms and performance monitoring interrupt generation a global interrupt (pin ad8) may be generated if enabled by register greg1. this interrupt is clocked using chan- nel 1 framer receive line clock (rlck1). if rlck1 is absent, the interrupt is clocked using rlck2, the receive line clock of channel 2. if both rlck1 and rlck2 are absent, clocking of interrupts is controlled by an interval 2.048 mhz clock generated from the chi clock. timing of the interrupt is shown in figure 25. there is no relation between mpck (pin ae10) and the interrupt, i.e., mpck maybe asynchronous with any of the other TFRA08C13 clocks. 5-6563(f).ar.1 figure 25. relation between rlck1 and interrupt (pin ad8) alarm definition the receive framer monitors the receive line data for alarm conditions and errored events, and then presents this information to the system through the microprocessor interface status registers. the transmit framer, to a lesser degree, monitors the receive system data and presents the information to the system through the microprocessor interface status registers. updating of the status registers is controlled by the receive line clock signal. when the receive loss of clock monitor determines that the receive line clock signal is lost, the system clock is used to clock the status registers and all status information should be considered corrupted. although the precise method of detecting or generating alarm and error signals differs between framing modes, the functions are essentially the same. the alarm conditions monitored on the received line interface are: n red alarm or the loss of frame alignment indication (frm_sr1 bit 0). the red alarm indicates that the receive frame alignment for the line has been lost and the data cannot be properly extracted. the red alarm is indicated by the loss of frame condition for the various framing formats as defined in table 26. rlck1 interrupt (pin ad8) preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 68 lucent technologies inc. lucent technologies inc. alarms and performance monitoring (continued) table 26. red alarm or loss of frame alignment conditions n yellow alarm or the remote frame alarm (frm_sr1 bit 0). this alarm is an indication that the line remote end is in a loss of frame alignment state. indication of remote frame alarm (commonly referred to as a yellow alarm) as for the different framing formats is shown in table 27. table 27. remote frame alarm conditions n blue alarm or the alarm indication signal (ais). the alarm indication signal (ais), sometimes referred to as the blue alarm, is an indication that the remote end is out-of-service. detection of an incoming alarm indication signal is defined in table 29. framing format number of errored framing bits that will cause a red alarm (loss of frame alignment) condition d4 2 errored frame bits (f t or f s ) out of 4 consecutive frame bits if frm_pr10 bit 2 = 1. 2 errored f t bits out of 4 consecutive f t bits if prm_pr10 bit 2 = 0. slc -96 2 errored frame bits (f t or f s ) out of 4 consecutive frame bits if frm_pr10 bit 2 = 1. 2 errored f t bits out of 4 consecutive f t bits if frm_pr10 bit 2 = 0. dds: frame 3 errored frame bits (f t or f s ) or channel 24 fas pattern out of 12 consecutive frame bits. esf 2 errored f e bits out of 4 consecutive f e bits or, optionally, 320 or more crc6 errored checksums within a one second interval if loss of frame alignment due to excessive crc-6 errors is enabled in frm_pr9. cept three consecutive incorrect fas patterns or three consecutive incorrect not fas patterns; or optionally, greater than 914 received crc-4 checksum errors in a one second interval if loss of frame alignment due to excessive crc-6 errors is enabled in frm_pr9. framing format remote frame alarm format superframe: d4 bit 2 of all time slots in the 0 state. superframe: d4-japanese the twelfth (12th) framing bit in the 1 state in two out of three consecutive super- frames. superframe: dds bit 6 of time slot 24 in the 0 state. extended superframe (esf) an alternating pattern of eight ones followed by eight 0s in the esf data link. cept: basic frame bit 3 of the not fas frame in the 1 state in three consecutive frames. cept: signaling multiframe bit 6 of the time slot 16 signaling frame in the 1 state. lucent technologies inc. 69 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. alarms and performance monitoring (continued) table 28. alarm indication signal conditions n the slip condition (frm_sr3 bit 6 and bit 7). slip is defined as the state in which the receive elastic store buffers write address pointer from the receive framer and the read address pointer from the transmit concentra- tion highway interface are equal * . the negative slip (slip-n) alarm indicates that the receive line clock (rlck) - transmit chi clock (chick) monitoring circuit detects a state of overflow caused by rlck and chick being out of phase-lock and the period of the received frame being less than that of the system frame. one system frame is deleted. the positive slip (slip-p) alarm indicates the line clock (rlck) - transmit chi clock (chick) monitoring circuit detects a state of underflow caused by rlck and chick being out of phase-lock and the period of the received frame being greater than that of the system frame. one system frame is repeated. n the loss of framer receive clock (lorlck, pin g23). the lorlck alarm is asserted high when an interval of 250 ms has expired with no transition of rlck (pin see table 2. pin descriptions) detected. the alarm is dis- abled on the first transition of rlck. bit 0bit 2 of global register 8 (greg8) determine which framer sources the lorlck pin (see table 69 interrupt status register (frm_sr0) (y00)). n the loss of pll clock (lopllck, pin f25). lopllck alarm is asserted high when an interval of 250 ms has expired with no transition of pllck (pin see table 2 . pin descriptions) detected. the alarm is disabled 250 s after the first transition of pllck. timing for lopllck is shown in figure 26. bit 0bit 2 of global register 8 (greg8) determine which framer sources the lopllck pin (see table 69). 5-6564(f).a figure 26. timing for generation of lopllck (pin f25) * after a reset, the read and write pointers of the receive path elastic store will be set to a known state. framing format remote frame alarm format t1 loss of frame alignment occurs and the incoming signal has two or fewer zeros in each of two consecutive double frame periods (386 bits). cept etsi as described in etsi ets 300 233: may 1994, section 8.2.2.4, loss of frame alignment occurs and the framer receives a 512 bit period containing two or less binary zeros. this is enabled by setting register frm_pr10 bit 1 to 0. cept itu as described in itu rec. g.775, the incoming signal has two or fewer zeros in each of two consecutive double frame periods (512 bits). ais is cleared if each of two consecutive double frame periods contains three or more zeros or frame alignment signal (fas) has been found. this is enabled by setting register frm_pr10 bit 1 to 1. pllck lopllck chick 250 m s 250 m s preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 70 lucent technologies inc. lucent technologies inc. alarms and performance monitoring (continued) n received bipolar violation errors alarm, frm_sr3 bit 0. this alarm indicates any bipolar decoding error or detection of excessive zeros. n received excessive crc errors alarm, frm_sr3 bit 3. in esf, this alarm is asserted when 320 or more crc-6 checksum errors are detected within a one second interval. in cept, this alarm is asserted when 915 or more crc-4 checksum errors are detected within a one second interval. n the cept continuous e-bit alarm (crebit) (frm_sr2 bit 2). crebit is asserted when the receive framer detects the following: five consecutive seconds where each 1 s interval contains 3 991 received e bits = 0 events. simultaneously no lfa occurred. optionally, no remote frame alarm (a bit = 1) was detected if register frm_pr9 bit 0, bit 4, and bit 5 are set to 1. optionally, neither sa6-f hex nor sa6-e hex codes were detected if register frm_pr9 bit 0, bit 4, and bit 6 are set to 1. the 5 s timer is started when the following occurs: crc-4 multiframe alignment is achieved. and optionally, a = 0 is detected if register frm_pr9 bit 0, bit 4, and bit 5 are set to 1. and optionally, neither sa6 _ f hex * nor sa6 _ e hex * is detected if register frm_pr9 bit 0, bit 4, and bit 6 are set to 1. the 5 s counter is restarted when the following occurs: lfa occurs, or 3 990 e bit = 0 events occur in 1 s, or optionally, an a bit = 1 is detected if register frm_pr9 bit 0, bit 4, and bit 5 are set to 1. optionally, a valid sa6 pattern 1111 (binary) or sa6 pattern 1110 (binary) code was detected if register frm_pr9 bit 0, bit 4, and bit 6 are set to 1. this alarm is disabled during loss of frame alignment (lfa) or loss of crc-4 multiframe alignment (lts0mfa). n failed state alarm or the unavailable state alarm , frm_sr5 bit 3 and bit 7 and frm_sr6 bit 3 and bit 7. this alarm is defined as the unavailable state at the onset of ten consecutive severely errored sec- onds. in this state, the receive framer inhibits incre- menting of the severely errored and errored second counters for the duration of the unavailable state. the receive framer deasserts the unavailable state condi- tion at the onset of ten consecutive errored seconds which were not severely errored. n the 4-bit sa6 codes (frm_sr2 bit 3bit 7). sa6 codes are asserted if three consecutive 4-bit pat- terns have been detected. the alarms are disabled when three consecutive 4-bit sa6 codes have been detected that are different from the pattern previously detected. the receive framer monitors the sa6 bits for special codes described in etsi ets 300 233: may 1994, section 9.2. the sa6 codes are defined in table 29 and table 30. the sa6 codes in table 29 may be recognized as an asynchronous bit stream in either non-crc-4 or crc-4 modes as long as the receive framer is in the basic frame alignment state. in the crc-4 mode, the receive framer can optionally recognize the received sa6 codes in table 29 syn- chronously to the crc-4 submultiframe structure as long as the receive framer is in the crc-4 multiframe alignment state (synchronous sa6 monitoring can be enabled by setting register frm_pr10 bit 1 to 1). the sa6 codes in table 30 are only recognized syn- chronously to the crc-4 submultiframe and when the receive framer is in crc-4 multiframe alignment. the detection of three (3) consecutive 4-bit patterns are required to indicate a valid received sa6 code. the detection of sa6 codes is indicated in status reg- ister frm_sr2 bit 3bit 7. once set, any three-nib- ble (12-bit) interval that contains any other sa6 code will clear the current sa6 status bit. interrupts may be generated by the sa6 codes given in table 29 * see table 29, for the definition of this sa6 pattern. lucent technologies inc. 71 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. alarms and performance monitoring (continued) table 29. sa6 bit coding recognized by the receive framer table 30 defines the three 4-bit sa6 codes that are always detected synchronously to the crc-4 submultiframe structure, and are only used for counting nt1 events. table 30. sa6 bit coding of nt1 interface events recognized by the receive framer the reference points for receive crc-4, e-bit, and sa6 decoding are illustrated in figure 27 code first receive bit (msb) last received bit (lsb) sa6_8 hex 100 0 sa6_a hex 101 0 sa6_c hex 110 0 sa6_e hex 111 0 sa6_f hex 111 1 code first receive bit (msb) last received bit (lsb) event at nt1 counter size (bits) sa6_1 hex 000 1 e = 0 16 sa6_2 hex 0 0 1 0 crc-4 error 16 sa6_3 hex 0 0 1 1 crc-4 error & e = 0 this code will cause both counters to increment. preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 72 lucent technologies inc. lucent technologies inc. alarms and performance monitoring (continued) 5-3913(f)r.8 figure 27. the t and v reference points for a typical cept e1 application n cept auxiliary pattern alarm (auxp) (frm_sr1 bit 6). the received auxiliary alarm, register frm_sr1 bit 6 (auxp), is asserted when the receive framer is in the lfa state and has detected more than 253 10 (binary) pat- terns for 512 consecutive bits. in a 512-bit interval, only two 10 (binary) patterns are allowable for the alarm to be asserted and maintained. the 512-bit interval is a sliding window determined by the first 10 (binary) pattern detected. this alarm is disabled when three or more 10 (binary) patterns are detected in 512 consecutive bits. the search for auxp is synchronized with the first alternating 10 (binary) pattern as shown in table 31. table 31. auxp synchronization and clear sychronization process 00 10 10 01 11 11 00 00 0 10 00 10 sync clear sync sync . . . . . . nt2 e bit = 0 nt1 et v reference e bit = 0, error event detected at the nt1 remote crc-4 errors at the nt1 e bit = 0, error event at the et remote crc-4 errors at the et, crc-4 errors detected from nt1 remote, then set sa6 = 001x e = 0 detected from nt1 remote, then set sa6 = 00x1 point t reference point count: 1) crc errors, 2) e = 0, 3) sa6 = 001x, and 4) sa6 = 00x1 sa6 crc error detected crc error detected (nt1 remote) e bit = 0 lucent technologies inc. 73 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. alarms and performance monitoring (continued) event counters definition the error events monitored in the receive framers status registers are defined in table 32 for the hardwired (default) threshold values. the errored second and severely errored second threshold registers can be pro- grammed through frm_pr11frm_pr13 such that the errored and severely errored second counters function as required by system needs. ds1 errors are reported in the et error registers, frm_sr20 through frm_sr35. for the framer to correctly report coding and bpv errors, the liu/framer interface must be configured as dual rail mode. table 32. event counters definition error event functional mode definition counter size (bits) bipolar violations (bpvs) ami any bipolar violation or 16 or more consecutive zeros 16 b8zs any bpv, code violation, or any 8-bit interval with no one pulse cept hdb3 any bpv, code violation, or any 4-bit interval with no one pulse frame alignment errors (fers) sf: d4 any f t or f s bit errors (frm_pr10 bit 2 = 1) or any f t bit errors (frm_pr10 bit 2 = 0) 16 sf: slc -96 any f t or f s bit errors (frm_pr10 bit 2 = 1) or any f t bit errors (frm_pr10 bit 2 = 0) sf: dds any f t , f s , or time slot 24 fas bit error esf any f e bit error cept any fas (0011011) or not fas (bit 2) bit error if register frm_pr10, bit 2 = 0. any fas (0011011) bit error if register frm_pr10, bit 2 = 1. crc checksum errors esf or cept with crc any received checksum in error 16 excessive crc errors esf 3 320 checksum errors in a one second interval none cept with crc 3 915 checksum errors in a one second interval received e bits = 0 cept with crc-4 e bits = 0 in frame 13 and frame 15 16 errored second events all any one of the relevant error conditions enabled in registers frm_pr14frm_pr18 within a one second interval 16 ds1: non-esf any framing bit errors within a one second interval ds1: esf any crc-6 errors within a one second interval cept without crc-4 any framing errors within a one second interval cept with crc-4 (et1) any crc-4 errors within a one second interval cept with crc-4 (et1 remote) any e bit = 0 event within a one second interval cept with crc-4 (nt1) any sa6 = 001x (binary) code event within a one second interval cept with crc-4 (nt1 remote) any sa6 = 00x1 (binary) code event within a one second interval preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 74 lucent technologies inc. lucent technologies inc. alarms and performance monitoring (continued) table 32. event counters definition (continued) the receive framer enters an unavailable state condition at the onset of ten consecutive severely errored second events. when in the unavailable state, the receive framer deasserts the unavailable state alarms at the onset of ten consecutive seconds which were not severely errored. error event functional mode definition counter size (bits) bursty errored second events ds1: non-esf greater than 1 but less than 8 framing bit errors within a one second interval 16 ds1: esf greater than 1 but less than 320 crc-6 errors within a one second interval cept without crc-4 greater than 1 but less than 16 framing bit errors within a one second interval cept with crc-4 (et1) greater than 1 but less than 915 crc-4 errors within a one second interval cept with crc-4 (et1 remote) greater than 1 but less than 915 e bit = 0 events within a one second interval cept with crc-4 (nt1) greater than 1 but less than 915 sa6=001x (binary) code events within a one second interval cept with crc-4 (nt1 remote) greater than 1 but less than 915 sa6=00x1 (binary) code events within a one second interval severely errored second events all any one of the relevant error conditions enabled in registers frm_pr14frm_pr18 within a one second interval 16 ds1: non-esf 8 or more framing bit errors within a one second interval ds1: esf 320 or more crc-6 errors within a one second interval cept with no crc-4 16 or more framing bit errors within a one second interval cept with crc-4 (et1) 915 or more crc-4 errors within a one second interval cept with crc-4 (et1 remote) 915 or more e bit = 0 events within a one second interval cept with crc-4 (nt1) 915 or more sa6=001x (binary) code events within a one second interval cept with crc-4 (nt1 remote) 915 or more sa6=00x1 (binary) code events within a one second interval unavailable second events all a one second period in the unavailable state 16 lucent technologies inc. 75 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. alarms and performance monitoring (continued) loopback and transmission modes primary loopback modes framer primary loopback mode is controlled by register frm_pr24. there are seven primary loopback and transmission test modes supported: n line loopback (llb). n board loopback (blb). n single time-slot system loopback (stsslb). n single time-slot line loopback (stsllb). n cept nailed-up broadcast transmission (cnubt). n payload loopback (pllb). n cept nailed-up connect loopback (cnuclb). the loopback and transmission modes are described in detail below: n the llb mode loops the receive line data and clock back to the transmit line. the received data is pro- cessed by the receive framer and transmitted to the system interface. this mode can be selected by set- ting register frm_pr24 to 001xxxxx (binary). n the blb mode loops the receive system data back to the system after: the transmit framer processes the data, and the receive framer processes the data. in the blb mode, ais is always transmitted to the line interface. this mode can be selected by setting register frm_pr24 to 010xxxxx (binary). n the stsslb mode loops one and only one received system time slot back to the transmit system inter- face. the selected looped back time-slot data is not processed by either the transmit framer or the receive framer. the selected time slot does not pass through the receive elastic store buffer and therefore will not be affected by system-ais, rlfa conditions, or controlled slips events. once selected, the desired time-slot position has the programmable idle code in register frm_pr22 transmitted to the line interface one frame before implementing the loopback and for the duration of the loopback. this mode can be selected by setting register frm_pr24 to 011a 4 a 3 a 2 a 1 a 0 , where a 4 a 3 a 2 a 1 a 0 is the binary address of the selected time slot. n the stsllb mode loops one and only one received line time slot back to the transmit line. the selected time-slot data is looped to the line after being pro- cessed by the receive framer, and it passes through the receive elastic store. the selected time slot has the programmable idle code in register frm_pr22 transmitted to the system interface one frame before implementing the loopback and for the duration of the loopback. in cept, selecting time slot 0 has the effect of deactivating the current loopback mode while no other action will be taken (time slot 0 will not be looped back to the line and should not be cho- sen). this mode can be selected by setting register frm_pr24 to 100a 4 a 3 a 2 a 1 a 0 , where a 4 a 3 a 2 a 1 a 0 is the binary address of the selected time slot. n the cnubt mode transmits received-line time slot x to the system in time slot x and time slot 0 (of the next frame). any time slot can be broadcast. this mode can be selected by setting register frm_pr24 to 101a 4 a 3 a 2 a 1 a 0 where a 4 a 3 a 2 a 1 a 0 is the binary address of the selected time slot. n the pllb mode loops the received line data and clock back to the transmit line while inserting (replac- ing) the facility data link in the looped back data. two variations of the payload loopback are available. in the pass-through framing/crc bit mode (chosen by setting register frm_pr24 to 111xxxxx (binary)), the framing and crc bits are looped back to the line transmit data. in the regenerated framing/crc bit mode (chosen by setting register frm_pr24 to 110xxxxx (binary) and register frm_pr10 bit 3 to 0), the framing and crc bits are regenerated by the transmit framer. the payload loopback is only available for esf and cept modes. n the cnuclb mode loops received system time slot x back to the system in time slot 0. the selected time slot is not routed through the receive elastic store buffer and, therefore, will not be affected by system- ais, rlfa conditions, or controlled slips. any time slot can be looped back to the system. time slot x transmitted to the line is not affected by this loopback mode. looping received system time slot 0 has no effect on time slot 0 transmitted to the line, i.e., the transmit framer will always overwrite the fas and not fas data in time slot 0 transmitted to the line. this mode can be selected by setting register frm_pr24 to 110a 4 a 3 a 2 a 1 a 0 and register frm_pr10 bit 3 to 1, where a 4 a 3 a 2 a 1 a 0 is the binary address of the selected time slot. preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 76 lucent technologies inc. lucent technologies inc. alarms and performance monitoring (continued) secondary loopback modes there are two secondary loopback modes supported: n secondary-single time-slot system loopback (s-stsslb). n secondary-single time-slot line loopback (s-stsllb). the loopbacks are described in detail below: n the secondary-stsslb mode loops one and only one received system time slot back to the transmit system interface. the selected time-slot data looped back is not processed by either the transmit framer or the receive framer. the selected time slot does not pass through the receive elastic store buffer and therefore will not be affected by system-ais, rlfa conditions, or controlled slips events. whenever the secondary loopback register is programmed to the same time slot as the primary register, the primary loopback mode will control that time slot. once selected, the desired time-slot position has the programmable line idle code in register frm_pr22 transmitted to the line interface one frame before implementing the loopback and for the duration of the loopback. n the secondary-stsllb mode loops one and only one line time slot back to the line. the selected time slot data is looped to the line after being processed by the receive framer and it passes through the receive elastic store. the selected time slot has the programmable idle code in register frm_pr22 transmitted to the system inter- face one frame before implementing the loopback and for the duration of the loopback. in cept, selecting time slot 0 has the effect of deactivating the current loopback mode while no other action will be taken (time slot 0 will not be looped back to the line and should not be chosen in this mode). table 33 defines the deactivation of the two secondary loopback modes as a function of the activation of the pri- mary loopback and test transmission modes. table 33. summary of the deactivation of sstsslb and sstsllb modes as a function of activating the primary loopback modes primary loopback mode deactivation of s-stsslb deactivation of s-stsllb stsslb if primary time slot = secondary if primary time slot = secondary stsllb if primary time slot = secondary if primary time slot = secondary blb always always cnubt if the secondary time slot is ts0 or if the primary time slot = secondary if primary time slot = secondary llb always always nuclb if the secondary time slot is ts0 or if the primary time slot = secondary if primary time slot = secondary pllb always always lucent technologies inc. 77 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. alarms and performance monitoring (continued) figure 28 illustrates the various loopback modes implemented by each framer unit. 5-3914(f).d figure 28. loopback and test transmission modes framer framer line es system (3) single time-slot system loopback framer line es system (2) board loopback ais receive system data line system (1) line loopback is ignored insert only time slot x line es system (4) single time-slot line loopback transmit programmable idle code in register frm_pr22 line es system (5) cept nailed-up broadcast transmission transmit line ts-x in system ts-x and system ts-0 framer line es system (7) cept nailed-up connect loopback loopback ts-x in ts-0 transmit framer line system (6) payload line loopback transmit programmable line idle code in register frm_pr22 loopback ts-x in outgoing system ts-x in outgoing line ts-x preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 78 lucent technologies inc. lucent technologies inc. alarms and performance monitoring (continued) line test patterns test patterns may be transmitted to the line through either register frm_pr20 or register frm_pr69. only one of these sources may be active at the same time. signaling must be inhibited while sending these test patterns. transmit line test patternsusing register frm_pr20 the transmit framer can be programmed through register frm_pr20 to transmit various test patterns. these test patterns, when enabled, overwrite the received chi data. the test patterns available using register frm_pr20 are: n the unframed-ais pattern which consists of a continuous bit stream of ones (. . . 111111 . . .) enabled by setting register frm_pr20 bit 0 to 1. n the unframed-auxiliary pattern which consists of a continuous bit stream of alternating ones and 0s (. . . 10101010 . . .) enabled by setting register frm_pr20 bit 1 to 1. n the quasi-random test signal, enabled by setting register frm_pr20 bit 3 to 1, which consists of the following: a pattern produced by means of a 20-stage shift register with feedback taken from the seventeenth and twen- tieth stages via an exclusive-or gate to the first stage. the output is taken from the twentieth stage and is forced to a 1 state whenever the next 14 stages (19 through 6) are all 0. the pattern length is 1,048,575 or 2 20 C 1 bits. this pattern is described in detail in at&t technical reference 62411 [5] appendix and illustrated in figure 29. valid framing bits. valid transmit facility data link (tfdl) bit information. valid crc bits. 5-3915(f).dr.1 figure 29. 20-stage shift register used to generate the quasi-random signal n the pseudorandom test pattern, enabled by setting register frm_pr20 bit 2 to 1, which consists of: a 2 15 C 1 pattern inserted in the entire payload (time slots 124 in ds1 and time slots 132 in cept), as described by itu rec. 0.151 and illustrated in figure 30. valid framing pattern. valid transmit facility data link (tfdl) bit data. valid crc bits. d d-type flip-flops #1 dd #2 #17 d #18 dd #19 #20 a b c xor #6 #19 nor #20 quasi-random test output or lucent technologies inc. 79 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. alarms and performance monitoring (continued) 5-3915(f).er.1 figure 30. 15-stage shift register used to generate the pseudorandom signal n the idle code test pattern, enabled by setting register frm_pr20 bit 6 to 1, which consists of the following: the programmable idle code, programmed through register frm_pr22, in time slots 124 in ds1 and 031 in cept. valid framing pattern. valid transmit facility data link (tfdl) bit data. valid crc bits. transmit line test patternsusing register frm_pr69 framed or unframed patterns indicated in table 34 may be generated and sent to the line by register frm_pr69 and by setting register frm_pr20 to 00 (hex). selection of transmission of either a framed or unframed test pat- tern is made through frm_pr69 bit 3. if one of the test patterns of register frm_pr69 is enabled, a single bit error can be inserted into the transmitted test pattern by toggling register frm_pr69 bit 1 from 0 to 1. table 34. register frm_pr69 test patterns pattern register frm_pr69 bit 7 bit 6 bit 5 bit 4 mark (all ones ais) 0 0 0 0 qrss (2 20 C 1 with zero suppression) 0 0 0 1 2 5 C 1 0 0 1 0 63 (2 6 C 1) 0 0 1 1 511 (2 9 C 1) 0 1 0 0 511 (2 9 C 1) reversed 0 1 0 1 2047 (2 11 C 1) 0 1 1 0 2047 (2 11 C 1) reversed 0 1 1 1 2 15 C 1 1 0 0 0 2 20 C 1 1 0 0 1 2 20 C 1 1 0 1 0 2 23 C 1 1 0 1 1 1:1 (alternating) 1 1 0 0 d xor d-type flip-flops #1 dd #2 #3 d #13 dd #14 #15 a b c pseudorandom test output preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 80 lucent technologies inc. lucent technologies inc. alarms and performance monitoring (continued) receive line pattern monitorusing register frm_sr7 the receive framer pattern monitor continuously monitors the received line, detects the following fixed framed pat- terns, and indicates detection in register frm_sr7 bit 6 and bit 7. n the pseudorandom test pattern as described by itu rec. o.151 and illustrated in figure 30. detection of the pattern is indicated by register frm_sr7 bit 6 = 1. n the quasi-random test pattern described in at&t technical reference 62411[5] appendix and illustrated in fig- ure 29. detection of the pattern is indicated by register frm_sr7 bit 7 = 1. in ds1 mode, the received 193 bit frame must consist of 192 bits of pattern plus 1 bit of framing information. in cept mode, the received 256 bit frame must consist of 248 bits of pattern plus 8 bits (ts0) of framing information. no signaling, robbed bit in the case of t1 and ts16 signaling in the case of cept, may be present for successful detection of these two test patterns. to establish lock to the pattern, 256 sequential bits must be received without error. when lock to the pattern is achieved, the appropriate bit of register frm_sr7 is set to a 1. once pattern lock is established, the monitor can withstand up to 32 single bit errors per frame without a loss of lock. lock will be lost if more than 32 errors occur within a single frame. when such a condition occurs, the appropriate bit of register frm_sr7 is deasserted. the monitor then resumes scanning for pattern candidates. receive line pattern detectorusing register frm_pr70 framed or unframed patterns indicated in table 35 may be detected using register frm_pr70. detection of the selected test pattern is indicated when register frm_sr7 bit 4 is set to 1. selection of a framed or unframed test pattern is made through frm_pr70 bit 3. bit errors in the received test pattern are indicated when register frm_sr7 bit 5 = 1. the bit errors are counted and reported in registers frm_sr8 and frm_sr9, which are nor- mally the bpv counter registers. (in this test mode, the bpv counter registers do not count bpvs but count only bit errors in the received test pattern.) table 35. register frm_pr70 test patterns pattern register frm_pr70 bit 7 bit 6 bit 5 bit 4 mark (all ones ais) 0 0 0 0 qrss (2 20 C 1 with zero suppression) 0 0 0 1 2 5 C 1 0 0 1 0 63 (2 6 C 1) 0 0 1 1 511 (2 9 C 1) 0 1 0 0 511 (2 9 C 1) reversed 0 1 0 1 2047 (2 11 C 1) 0 1 1 0 2047 (2 11 C 1) reversed 0 1 1 1 2 15 C 1 1 0 0 0 2 20 C 1 1 0 0 1 2 20 C 1 1 0 1 0 2 23 C 1 1 0 1 1 1:1 (alternating) 1 1 0 0 lucent technologies inc. 81 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. alarms and performance monitoring (continued) the pattern detector continuously monitors the received line for the particular pattern selected in register frm_pr70 bit 7bit 4 (dptrn). to establish detector lock to the pattern, 256 sequential bits must be detected. once the detector has locked onto the selected pattern, it will remain locked to the established alignment and count all unexpected bits as single bit errors until register frm_pr70 bit 2 (dblksel) is set to 0. to select a pattern or change the pattern to be detected, the following programming sequence must be followed: n dblksel (register frm_pr70 bit 2) is set to 0. n the new pattern to be detected is selected by setting register frm_pr70 bit 7bit 4 to the desired value. n dblksel (register frm_pr70 bit 2) is set to 1. preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 82 lucent technologies inc. lucent technologies inc. alarms and performance monitoring (continued) automatic and on-demand commands various alarms can be transmitted either automatically as a result of various alarm conditions or on demand. after reset, all automatic transmissions are disabled. the user can enable the automatic or on-demand actions by set- ting the proper bits in the automatic and on-demand action registers as identified below in table 36. table 37 shows the programmable automatically transmitted signals and the triggering mechanisms for each. table 37 shows the on-demand commands. table 36. automatic enable commands action trigger enabling register bit transmit remote frame alarm (rfa) loss of frame alignment (rlfa) frm_pr27 bit 0 = 1 loss of cept time slot 16 multiframe alignment (rts16lmfa) frm_pr27 bit 1 = 1 loss of cept time slot 0 multiframe alignment (rts0lmfa) frm_pr27 bit 2 = 1 detection of the timer (100 ms or 400 ms) expiration due to loss of cept multiframe alignment frm_pr27 bit 3 = 1 frm_pr9 bit 7bit 0 = 0xxxx1x1 or 0xxx1xx1 detection of the cept rsa6 = 8 (hex) code frm_pr27 bit 4 = 1 detection of the cept rsa6 = c (hex) code frm_pr27 bit 5 = 1 transmit cept e bit = 0 detection of cept crc-4 error frm_pr28 bit 3 = 1 rts0lmfa frm_pr28 bit 4 = 1 detection of the timer (100 ms or 400 ms) expiration due to loss of cept multiframe alignment frm_pr28 bit 5 = 1 frm_pr9 bit 7bit 0 = 0xxxx1x1 or 0xxx1xx1 transmit ais to system rlfa frm_pr19 bit 0 = 1 detection of the timer (100 ms or 400 ms) expiration due to loss of cept multiframe alignment frm_pr19 bit 1 = 1 frm_pr9 bit 7bit 0 = 0xxxx1x1 or 0xxx1xx1 transmit cept time slot 16 remote multiframe alarm to line rts16lmfa frm_pr41 bit 4 = 1 transmit cept ais in time slot 16 to system rts16lmfa frm_pr44 bit 6 = 1 automatic enabling of ds1 line loopback on/off line loopback on/off code frm_pr19 bit 4 = 1 automatic enabling of esf fdl line loopback on/off esf line loopback on/off code frm_pr19 bit 6 = 1 automatic enabling of esf fdl payload loopback on/off esf payload loopback on/off code frm_pr19 bit 7 = 1 lucent technologies inc. 83 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. alarms and performance monitoring (continued) table 37. on-demand commands type frame format action enabling register bit transmit remote frame alarm d4 (japanese) f s bit in frame 12 = 1 frm_pr27 bit 6 = 1 d4 (us) bit 2 of all time slots = 0 frm_pr27 bit 7 = 1 dds bit 6 in time slot 24 = 0 esf pattern of 1111111100000000 in the fdl f-bit position cept a bit = 1 transmit time slot 16 remote multiframe alarm to the line cept time slot 16 remote alarm bit = 1 frm_pr41 bit 5 = 1 transmit data link ais (squelch) slc -96, esf transmit data link bit = 1 frm_pr21 bit 4 = 1 transmit line test patterns all transmit test patterns to the line interface see transmit line test patternsusing register frm_pr20 section on page 78 and transmit line test patternsusing reg- ister frm_pr69 section on page 79. transmit system ais all transmits ais to the system frm_pr19 bit 3 = 1 transmit system signaling ais (squelch) t1 transmit abcd = 1111 to the sys- tem frm_pr44 bit 1 = 1 cept transmit ais in system time slot 16 frm_pr44 bit 7 = 1 receive signaling inhibit all suspend the updating of the receive signaling registers frm_pr44 bit 3 = 1 receive framer reframe all force the receive framer to reframe frm_pr26 bit 2 = 1 transmit line time slot 16 cept transmit ais in time slot 16 to the line frm_pr41 bit 6 = 1 enable loopback all enables system and line loopbacks see loopback and trans- mission modes section on page 75. framer software reset all the framer and fdl are placed in the reset state for four rclk clock cycles. the framer parameter reg- isters are forced to the default value. frm_pr26 bit 0 = 1 framer software restart all the framer and fdl are placed in the reset state as long as this bit is set to 1. the framer parameter reg- isters are not changed from their programmed values. frm_pr26 bit 1 = 1 84 lucent technologies inc. preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 lucent technologies inc. facility data link data may be extracted from and inserted into the facility data link in slc -96, dds, esf, and cept framing for- mats. in cept, any one of the sa bits can be declared as the facility data link by programming register frm_pr43 bit 0bit 2. access to the fdl is made through: n the fdl pins (rfdl, rfdlck, tfdl, and tfdlck). figure 15 shows the timing of these signals. n the 64-byte fifo of the fdl hdlc block. fdl information passing through the fdl hdlc section may be framed in hdlc format or passed through transparently. 5-3910(f).cr.1 figure 31. TFRA08C13 facility data link access timing of the transmit and receive framer sections t8 t9 t9 t10 t11 t8: tfdlck cycle = t9: tfdl to tfdlck setup/hold = 40 ns t10: rfdlck cycle = t11: rfdlck to rfdl delay = 40 ns tfdlck tfdl rfdlck rfdl 250 m s (all other modes) 125 m s (dds) 250 m s (all other modes) 125 m s (dds) in the esf frame format, automatic assembly and transmission of the performance report message (prm) as defined in both ansi t1.403-1995 and te l - cordia technologies * tr-tsy-000194 issue 1, 1287 is managed by the receive framer and transmit fdl sections. the ansi t1.403-1995 bit-oriented data link messages (bom) can be transmitted by the transmit fdl section and recognized and stored by the receive fdl section. receive facility data link interface summary a brief summary of the receive facility data link func- tions is given below: n bit-oriented message (bom) operation. the ansi t1.403-1995 bit-oriented data link messages are recognized and stored in register fdl_sr3. the number of times that an ansi code must be received for detection can be programmed from 1 to 10 by writing to register fdl_pr0 bit 4 bit 7. when a valid ansi code is detected, register fdl_sr0 bit 7 (fransi) is set. n hdlc operation. this is the default mode of opera- tion when the fdl receiver is enabled (register fdl_pr1 bit 2 = 1). the hdlc framer detects the hdlc flags, checks the crc bytes, and stores the data in the fdl receiver fifo (register fdl_sr4) along with a status of frame (sf) byte. n hdlc operation with performance report mes- sages (prm). this mode is enabled by setting regis- ter fdl_pr1 bit 2 and bit 6 to 1. in this case, the receive fdl will store the 13 bytes of the prm report field in the fdl receive fifo (register fdl_sr4) along with a status of frame (sf) byte. n transparent operation. enabling the fdl and set- ting register fdl_pr9 bit 6 (ftm) to 1 disables the hdlc processing. incoming data link bits are stored in the fdl receive fifo (register fdl_sr4). * telcordia technologies is a registered trademark of bell communications research, inc. lucent technologies inc. 85 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. facility data link (continued) n transparent operation with pattern match. enabling the fdl and setting registers fdl_pr9 bit 5 (fmatch) and fdl_pr9 bit 6 (ftm) to 1 forces the fdl to start storing data in the fdl receive fifo (register fdl_sr4) only after the programmable match character defined in register fdl_pr8 bit 0bit 7 has been detected. the match character and all subsequent bytes are placed into the fdl receive fifo. the fdl interface to the receive framer is illustrated in figure 32. 5-4560(f).ar.1 figure 32. block diagram for the receive facility data link interface receive ansi t1.403 bit-oriented messages (bom) n the receive fdl monitor will detect any of the ansi t1.403 esf bit-oriented messages (boms) and generate an interrupt, enabled by register fdl_pr6 bit 7, upon detection. register fdl_sr0 bit 7 (fransi) is set to 1 upon detection of a valid bom and then cleared when read. n the received esf fdl bit-oriented messages are received in the form 111111110x 0 x 1 x 2 x 3 x 4 x 5 0 (the left most bit is received first). the bits designated as x are the defined ansi esf fdl code bits. these code bits are writ- ten into the received ansi fdl status register fdl_sr3 when the entire code is received. n the minimum number of times a valid code must be received before it is reported can be programmed from 1 to 10 using register fdl_pr0 bit 4bit 7. receive line data receive framer loss of frame alignment receive fdl data extracter rfdl rfdlck receive facili ty data ansi t1.403-1995 bit-oriented data link messages monitor one 8-bit register identifying the esf bit-oriented code transparent microprocessor interface receive facility data link fifo receive facility data link hdlc rfdl rfdlck 64 8-bit locations preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 86 lucent technologies inc. lucent technologies inc. facility data link (continued) the received ansi fdl status byte, register fdl_sr3, has the following format. table 38. receive ansi code receive ansi performance report messages (prm) as defined in ansi t1.403, the performance report messages consist of 15 bytes, starting and ending with an hdlc flag. the receive framer status information consists of four pairs of octets, as shown in table 39. upon detection of the prm message, the receive fdl extracts the 13 bytes of the prm report field and stores it in the receive fdl fifo along with the status of frame byte. table 39. performance re p ort messa g e structure * * the rightmost bit (bit 1) is transmitted first for all fields except for the 2 bytes of the fcs that are transmitted left most bit (bit 8) first. the definition of each prm field is shown in table 40, and octet content is shown in table 41. b7 b6 b5 b4 b3 b2 b1 b0 00x 5 x 4 x 3 x 2 x 1 x 0 octet number prm b7 prm b6 prm b5 prm b4 prm b3 prm b2 prm b1 prm b0 1fla g 2sapic/rea 3 tei ea 4control 5 g3lvg4u1u2g5slg6 6 feselbg1 r g2nmnl 7 g3lvg4u1u2g5slg6 8 feselbg1 r g2nmnl 9 g3lvg4u1u2g5slg6 10 fe se lb g1 r g2 nm nl 11 g3 lv g4 u1 u2 g5 sl g6 12 fe se lb g1 r g2 nm nl 1314 fcs 15 fla g lucent technologies inc. 87 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. facility data link (continued) table 40 . fdl performance re p ort messa g e field definition table 41 . octet contents and definition prm field definition g1 = 1 crc error event = 1 g2 = 1 1 < crc error event 5 g3 = 1 5 < crc error event 10 g4 = 1 10 < crc error event 100 g5 = 1 100 < crc error event 319 g6 = 1 crc error event 3 320 se = 1 severel y errored framin g event 3 1 ( fe will = 0 ) fe =1 frame s y nchronization bit error event 3 1 ( se will = 0 ) lv = 1 line code violation event 3 1 sl = 1 slip event 3 1 lb = 1 pa y load loopback activated u1, u2 = 0 reserved r = 0 reserved ( default value = 0 ) nm, nl = 00, 01, 10, 11 one-second report modulo 4 counter octet number octet contents definition 1 01111110 openin g lapd fla g 2 00111000 00111010 from ci: sapi = 14, c/r = 0, ea = 0 from carrier: sapi = 14, c/r = 1, ea = 0 3 00000001 tei = 0, ea = 1 4 00000011 unacknowled g ed frame 5, 6 variable data for latest second ( t ) 7, 8 variable data for previous second ( t C 1 ) 9, 10 variable data for earlier second ( t C 2 ) 11, 12 variable data for earlier second ( t C 3 ) 13, 14 variable crc-16 frame check se q uence 15 01111110 closin g lapd fla g preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 88 lucent technologies inc. lucent technologies inc. facility data link (continued) receive hdlc mode this is the default mode of the fdl. the receive fdl receives serial data from the receive framer, identifies hdlc frames, reconstructs data bytes, provides bit destuffing as necessary, and loads parallel data in the receive fifo. the receive queue manager forms a status of frame (sf) byte for each hdlc frame and stores the sf byte in the receive fdl fifo (register fdl_sr4) after the last data byte of the associated frame. hdlc frames consisting of n bytes will have n + 1 bytes stored in the receive fifo. the frame check sequence bytes (crc) of the received hdlc frame are not stored in the receive fifo. when receiving ansi prm frames, the frame check sequence bytes are stored in the receive fifo. the sf byte has the following format. table 42. receive status of frame b y te bit 7 of the sf status byte is the crc status bit. a 1 indicates that an incorrect crc was detected. a 0 indicates the crc is correct. bit 6 of the sf status byte is the abort status. a 1 indicates the frame associated with this status byte was aborted (i.e., the abort sequence was detected after an opening flag and before a subsequent closing flag). an abort can also cause bits 7 and/or 4 to be set to 1. an abort is not reported when a flag is followed by seven ones. bit 5 is the fifo overrun bit. a 1 indicates that a receive fifo overrun occurred (the 64-byte fifo size was exceeded). bit 4 is the fifo bad byte count that indicates whether or not the bit count received was a multiple of eight (i.e., an integer number of bytes). a 1 indicates that the bit count received after 0-bit deletion was not a mul- tiple of eight, and a 0 indicates that the bit count was a multiple of eight. when a non-byte-aligned frame is received, all bits received are present in the receive fifo. the byte before the sf status byte contains less than eight valid data bits. the hdlc block provides no indication of how many of the bits in the byte are valid. user application programming controls processing of non-byte-aligned frames. bit 3bit 0 of the sf status byte are not used and are set to 0. a good frame is implied when the sf status byte is 00 (hex). receive fdl fifo whenever an sf byte is present in the receive fifo, the end of frame registers fdl_sr0 bit 4 (freof) and fdl_sr2 bit 7 (feof) bits are set. the receiver queue status (register fdl_sr2 bit 0bit 6) bits report the num- ber of bytes up to and including the first sf byte. if no sf byte is present in the receive fifo, the count directly reflects the number of data bytes available to be read. depending on the fdl frame size, it is possible for multiple frames to be present in the receive fifo. the receive fill level indicator register fdl_pr6 bit 0bit 5 (fril) can be programmed to tailor the service time interval to the system. the receive fifo full register fdl_sr0 bit 3 (frf) interrupt is set in the interrupt status register when the receive fifo reaches the preprogrammed full position. an freof interrupt is also issued when the receiver has identified the end of frame and has written the sf byte for that frame. an fdl overrun interrupt register fdl_sr0 bit 5 (froverun) is generated when the receiver needs to write either status or data to the receive fifo while the receive fifo is full. an overrun condition will cause the last byte of the receive fifo to be overwritten with an sf byte indicating the overrun status. a receive idle register fdl_sr0 bit 6 (fridl) interrupt is issued whenever 15 or more continuous ones have been detected. rsf b7 rsf b6 rsf b5 rsf b4 rsf b3 rsf b2 rsf b1 rsf b0 bad crc abort rfifo overrun bad byte count 0000 lucent technologies inc. 89 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. facility data link (continued) the receive queue status bits, register fdl_sr2 bit 0bit 6 (frqs), are updated as bytes are loaded into the receive fifo. the sf status byte is included in the byte count. when the first sf status byte is placed in the fifo, register fdl_sr0 bit 4 (freof) is set to 1, and the status freezes until the fifo is read. as bytes are read from the fifo, the queue status decrements until it reads 1. the byte read when register fdl_sr2 bit 0bit 6 = 0000001 and the freof bit is 1 is the sf status byte describing the error status of the frame just read. once the first sf status byte is read from the fifo, the fifo status is updated to report the number of bytes to the next sf status byte, if any, or the number of additional bytes present. when freof is 0, no sf status byte is currently present in the fifo, and the frqs bits report the number of bytes present. as bytes are read from the fifo, the queue status decre- ments with each read until it reads 0 when the fifo is totally empty. the freof bit is also 0 when the fifo is completely empty. thus, the frqs and freof bit pro- vide a mechanism to recognize the end of 1 frame and the beginning of another. reading the fdl receiver status register does not affect the fifo buffers. in the event of a receiver overrun, an sf status byte is written to the receive fifo. multiple sf status bytes can be present in the fifo. the frqs reports only the num- ber of bytes to the first sf status byte. if frqs is 0, do not read the receive fifo. a read will result in the cor- ruption of receive fifo. to allow users to tailor receiver fifo service intervals to their systems, the receiver interrupt level bits in reg- ister fdl_pr6 bit 0bit 5 (fril) are provided. these bits are coded in binary and determine when the receiver full interrupt, register fdl_sr0 bit 3 (frf), is asserted. the interrupt pin transition can be masked by setting register fdl_pr2 bit 3 (frfie) to 0. the value programmed in the fril bits equals the total number of bytes necessary to be present in the fifo to trigger an frf interrupt. the frf interrupt alone is not sufficient to determine the number of bytes to read, since some of the bytes may be sf status bytes. the frqs bits and freof bit allow the user to determine the number of bytes to read. the freof interrupt can be the only interrupt for the final frame of a group of frames, since the number of bytes received to the end of the frame cannot be sufficient to trigger an frf interrupt. programming note: since the receiver writing to the receive fifo and the host reading from the receive fifo are asynchronous events, it is possible for a host read to put the number of bytes in the receive fifo just below the programmed fril level and a receiver write to put it back above the fril level. this causes a new frf interrupt, and has the potential to cause software problems. it is recommended that during service of the frf interrupt, the frf interrupt be masked frfie = 0, and the interrupt register be read at the end of the ser- vice routine, discarding any frf interrupt seen, before unmasking the frf interrupt. receiver overrun a receiver overrun occurs if the 64-byte limit of the receiver fifo is exceeded, i.e., data has been received faster than it has been read out of the receive fifo. upon overrun, an sf status byte with the overrun bit (bit 5) set to 1 replaces the last byte in the fifo. the sf status byte can have other error conditions present. for example, it is unlikely the crc is correct. thus, care should be taken to prioritize the possible frame errors in the software service routine. the last byte in the fifo is overwritten with the sf status byte regard- less of the type of byte (data or sf status) being over- written. the overrun condition is reported in register fdl_sr0 bit 5 and causes the interrupt pin to be asserted if it is not masked (register fdl_pr2 bit 5 (frovie)). data is ignored until the condition is cleared and a new frame begins. the overrun condition is cleared by reading register fdl_sr0 bit 5 and read- ing at least 1 byte from the receive fifo. because mul- tiple frames can be present in the fifo, good frames as well as the overrun frame can be present. the host can determine the overrun frame by looking at the sf status byte. preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 90 lucent technologies inc. lucent technologies inc. facility data link (continued) transmit facility data link interface the fdl interface of the transmit framer is shown in figure 33, indicating the priority of the fdl sources. the remote frame alarm, enabled using register frm_pr27, is given the highest transmission priority by the trans- mit framer. the ansi t1.403-1995 bit-oriented data link message transmission is given priority over performance report mes- sages and the automatic transmission of the performance report messages is given priority over fdl hdlc trans- mission. idle code is generated by the fdl unit when no other transmission is enabled. the fdl transmitter is enabled by setting register fdl_pr1 bit 3 to 1. 5-4561(f).a figure 33. block diagram for the transmit facility data link interface trans mit ansi t1.403 bit-oriented messages (bom) when the ansi bom mode is enabled by setting register fdl_pr10 bit 7 to 1, the transmit fdl can send any of the ansi t1.403 esf bit-oriented messages automatically through the fdl bit in the frame. the transmit esf fdl bit-oriented messages of the form 111111110x 0 x 1 x 2 x 3 x 4 x 5 0 are taken from the transmit ansi fdl parameter register fdl_pr10 bit 0bit 5. the esf fdl bit-oriented messages will be repeated while register fdl_pr10 bit 7 (ftansi) is set to 1. microprocessor interface transmit fdl fifo receive framer transmit fdl hdlc framer transmit fdl clock generator transparent tfdl tfdlck tfdlck transmit performance report message assembler transmit ansi t1.403 fdl bit code generator fdl idle code generator fdl yellow alarm transmit frame assembler lucent technologies inc. 91 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. facility data link (continued) tra nsmit ansi performance report messages (prm) when the ansi prm mode is enabled by setting register fdl_pr1 bit 7 to 1, the transmit fdl assembles and transmits the ansi performance report message once every second. after assembling the ansi prm message, the receive framer stores the current second of the message in regis- ters frm_sr62 and frm_sr63 and transfers the data to the fdl transmit fifo. after accumulating three sec- onds (8 bytes) of the message, the fdl transmit block appends the header and the trailer (including the opening and closing flags) to the prm messages and transmits it to the framer for transmission to the line. table 39table 41 show the complete format of the prm hdlc packet. hdlc operation hdlc operation is the default mode of operation. the transmitter accepts parallel data from the transmit fifo, con- verts it to a serial bit stream, provides bit stuffing as necessary, adds the crc-16 and the opening and closing flags, and sends the framed serial bit stream to the transmit framer. hdlc frames on the serial link have the follow- ing format. table 43 . hdlc frame format all bits between the opening flag and the crc are considered user data bits. user data bits such as the address, control, and information fields for lapb or lapd frames are fetched from the transmit fifo for transmission. the 16 bits preceding the closing flag are the frame check sequence, cyclic redundancy check (crc), bits. zero-bit insertion/deletion (bit stuffing/destuffing) the hdlc protocol recognizes three special bit patterns: lags, aborts, and idles. these patterns have the common characteristic of containing at least six consecutive ones. a user data byte can contain one of these special pat- terns. transmitter zero-bit stuffing is done on user data and crc fields of the frame to avoid transmitting one of these special patterns. whenever five ones occur between flags, a 0 bit is automatically inserted after the fifth 1, prior to transmission of the next bit. on the receive side, if five successive ones are detected followed by a 0, the 0 is assumed to have been inserted and is deleted (bit destuffing). opening flag user data field frame check sequence (crc) closing flag 01111110 3 8 bits 16 bits 01111110 preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 92 lucent technologies inc. lucent technologies inc. facility data link (continued) flags * all flags have the bit pattern 01111110 and are used for frame synchronization. the fdl hdlc block automati- cally sends two flags between frames. if the chip-con- figuration register fdl_pr0 bit 1 (flags) is cleared to 0, the ones idle byte (11111111) is sent between frames if no data is present in the fifo. if flags is set to 1, the fdl hdlc block sends continuous flags when the transmit fifo is empty. the fdl hdlc does not transmit consecutive frames with a shared flag; there- fore, two successive flags will not share the intermedi- ate 0. an opening flag is generated at the beginning of a frame (indicated by the presence of data in the transmit fifo and the transmitter enable register fdl_pr1 bit 3 = 1). data is transmitted per the hdlc protocol until a byte is read from the fifo while register fdl_pr3 bit 7 (ftfc) set to 1. the fdl hdlc block follows this last user data byte with the crc sequence and a clos- ing flag. the receiver recognizes the 01111110 pattern as a flag. two successive flags may or may not share the intermediate 0 bit and are identified as two flags (i.e., both 011111101111110 and 0111111001111110 are recognized as flags by the fdl hdlc block). when the second flag is identified, it is treated as the closing flag. as mentioned above, a flag sequence in the user data or crc bits is prevented by zero-bit insertion and dele- tion. the hdlc receiver recognizes a single flag between frames as both a closing and opening flag. aborts an abort is indicated by the bit pattern of the sequence 01111111. a frame can be aborted by writing a 1 to register fdl_pr3 bit 6 (ftabt). this causes the last byte written to the transmit fifo to be replaced with the abort sequence upon transmission. once a byte is tagged by a write to ftabt, it cannot be cleared by subsequent writes to register fdl_pr3. ftabt has higher priority than fdl transmit frame complete (ftfc), but ftabt and ftfc should never be set to 1 simultaneously since this causes the transmitter to enter an invalid state requiring a transmitter reset to clear. a frame should not be aborted in the very first byte following the opening flag. an easy way to avoid this situation is to first write a dummy byte into the queue and then write the abort command to the queue. when receiving a frame, the receiver recognizes the abort sequence whenever it receives a 0 followed by seven consecutive ones. the receive fdl unit will abort a frame whenever the receive framer detects a loss of frame alignment. this results in the abort bit, and possibly the bad byte count bit and/or bad crc bits, being set in the status of frame status byte (see table 42) which is appended to the receive data queue. all subsequent bytes are ignored until a valid opening flag is received. idles in accordance with the hdlc protocol, the hdlc block recognizes 15 or more contiguous received ones as idle. when the hdlc block receives 15 contiguous ones, the receiver idle bit register fdl_sr0 bit 6 (ridl) is set. for transmission, the ones idle byte is defined as the binary pattern 11111111 (ff (hex)). if the flags con- trol bit in register fdl_pr0 bit 1 is 0, the ones idle byte is sent as the time-fill byte between frames. a time-fill byte is sent when the transmit fifo is empty and the transmitter has completed transmission of all previous frames. frames are sent back-to-back otherwise. crc-16 for given user data bits, 16 additional bits that consti- tute an error-detecting code (crc-16) are added by the transmitter. as called for in the hdlc protocol, the frame check sequence bits are transmitted most signifi- cant bit first and are bit stuffed. the cyclic redundancy check (or frame check sequence) is calculated as a function of the transmitted bits by using the itu-t stan- dard polynomial: x 16 + x 12 + x 5 + 1 the transmitter can be instructed to transmit a cor- rupted crc by setting register fdl_pr2 bit 7 (ftb- crc) to 1. as long as the ftbcrc bit is set, the crc is corrupted for each frame transmitted by logically flip- ping the least significant bit of the transmitted crc. the receiver performs the same calculation on the received bits after destuffing and compares the results to the received crc-16 bits. an error indication occurs if, and only if, there is a mismatch. * regardless of the time-fill byte used, there always is an opening and closing flag with each frame. back-to-back frames are separated by two flags. lucent technologies inc. 93 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. facility data link (continued) transmit fdl fifo transmit fdl data is loaded into the 64-byte transmit fifo via the transmit fdl data register, fdl_pr4. the transmit fdl status register indicates how many addi- tional bytes can be added to the transmit fifo. the transmit fdl interrupt trigger level register fdl_pr3 bit 0bit 5 (ftil) can be programmed to tailor service time intervals to the system environment. the transmit- ter empty interrupt bit is set in the fdl interrupt status register fdl_sr0 bit 1 (ftem) when the transmit fifo has sufficient empty space to add the number of bytes specified in register fdl_pr3 bit 0bit 5. there is no interrupt indicated for a transmitter overrun that is writing more data than empty spaces exist. overrun- ning the transmitter causes the last valid data byte writ- ten to be repeatedly overwritten, resulting in missing data in the frame. data associated with multiple frames can be written to the transmit fifo by the controlling microprocessor. however, all frames must be explicitly tagged with a transmit frame complete, register fdl_pr3 bit 7 (ftfc), or a transmit abort, register fdl_pr3 bit 6 (ftabt). the ftfc is tagged onto the last byte of a frame written into the transmitter fifo and instructs the transmitter to end the frame and attach the crc and closing flag following the tagged byte. once written, the ftfc cannot be changed by another write to register fdl_pr3. if ftfc is not written before the last data byte is read out for transmission, an underrun occurs (fdl_sr0 bit 2). when the transmitter has completed a frame, with a closing flag or an abort sequence, reg- ister fdl_sr0 bit 0 (ftdone) is set to 1. an interrupt is generated if fdl_pr2 bit 0 (ftdie) is set to 1. sending 1-byte frames sending 1-byte frames with an empty transmit fifo is not recommended. if the fifo is empty, writing two data bytes to the fifo before setting ftfc provides a minimum of eight tfdlck periods to set ftfc. when 1 byte is written to the fifo, ftfc must be written within 1 tfdlck period to guarantee that it is effective. thus, 1-byte frames are subject to underrun aborts. one-byte frames cannot be aborted with ftabt. plac- ing the transmitter in ones-idle mode, register fdl_pr0 bit 1 (flags) = 0, lessens the frequency of underruns. if the transmit fifo is not empty, then 1-byte frames present no problems. transmitter underrun after writing a byte to the transmit queue, the user has eight tfdlck cycles in which to write the next byte before a transmitter underrun occurs. an underrun occurs when the transmitter has finished transmitting all the bytes in the queue, but the frame has not yet been closed by setting ftfc. when a transmitter underrun occurs, the abort sequence is sent at the end of the last valid byte transmitted. a ftdone interrupt is generated, and the transmitter reports an underrun abort until the interrupt status register is read. using the transmitter status and fill level the transmitter-interrupt level bits, register fdl_pr3 bit 0bit 5, allow the user to instruct the fdl hdlc block to interrupt the host processor whenever the transmitter has a predetermined number of empty loca- tions. the number of locations selected determines the time between transmitter empty, register frm_sr0 bit 1 (ftem), interrupts. the transmitter status bits, regis- ter fdl_sr1, report the number of empty locations in the fdl transmitter fifo. the transmitter empty dynamic bit, register fdl_sr1 bit 7 (fted), like the ftem interrupt bit, is set to 1 when the number of empty locations is less than or equal to the pro- grammed empty level. fted returns to 0 when the transmitter is filled to above the programmed empty level. polled interrupt systems can use fted to deter- mine when they can write to the fdl transmit fifo. transparent mode the fdl hdlc block can be programmed to operate in the transparent mode by setting register fdl_pr9 bit 6 (ftrans) to 1. in the transparent mode of operation, no hdlc processing is performed on user data. the transparent mode can be exited at any time by setting fdl_pr9 bit 6 (ftrans) to 0. it is recommended that the transmitter be disabled when changing in and out of transparent mode. the transmitter should be reset by setting fdl_pr1 bit 5 (ftr) to 1 whenever the mode is changed. 94 94 lucent technologies inc. preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 lucent technologies inc. facility data link (continued) in the transmit direction, the fdl hdlc takes data from the transmit fifo and transmits that data exactly bit-for-bit on the tfdl interface. transmit data is octet- aligned to the first tfdlck after the transmitter has been enabled. the bits are transmitted least significant bit first. when there is no data in the transmit fifo, the fdl hdlc either transmits all ones, or transmits the programmed hdlc transmitter idle character (register fdl_pr5) if register fdl_pr9 bit 6 (fmatch) is set to 1. to cause the transmit idle character to be sent first, the character must be programmed before the transmitter is enabled. the transmitter empty interrupt, register fdl_sr0 bit 1 (ftem), acts as in the hdlc mode. the transmitter- done interrupt, register fdl_sr0 bit 0 (ftdone), is used to report an empty fdl transmit fifo. the ftdone interrupt thus provides a way to determine transmission end. register fdl_sr0 bit 2 (ftund- abt) interrupt is not active in the transparent mode. in the receive direction, the fdl hdlc block loads received data from the rfdl interface directly into the receive fifo bit-for-bit. the data is assumed to be least significant bit first. if fmatch register fdl_pr9 bit 6 is 0, the receiver begins loading data into the receive fifo beginning with the first rfdlck detected after the receiver has been enabled. if the fmatch bit is set to 1, the receiver does not begin loading data into the fifo until the receiver match character has been detected. the search for the receiver match character is in a sliding window fashion if register fdl_pr9 bit 4 (faloct) bit is 0 (align to octet), or only on octet boundaries if faloct is set to 1. the octet boundary is aligned relative to the first rfdlck after the receiver has been enabled. the matched character and all sub- sequent bytes are placed in the receive fifo. an fdl receiver reset, register fdl_pr1 bit 4 (frr) = 1, causes the receiver to realign to the match character if fmatch is set to 1. the receiver full (frf) and receiver overrun (froverun) interrupts in register fdl_sr0 act as in the hdlc mode. the received end of frame (freof) and receiver idle (fridl) interrupts are not used in the transparent mode. the match status (fmstat) bit is set to 1 when the receiver match character is first rec- ognized. if the fmatch bit is 0, the fmstat (fdl_pr9 bit 3) bit is set to 1 automatically when the first bit is received, and the octet offset status bits (fdl_pr9 bit 0bit 2) read 000. if the fmatch bit is programmed to 1, the fmstat bit is set to 1 upon rec- ognition of the first receiver match character, and the octet offset status bits indicate the offset relative to the octet boundary at which the receiver match character was recognized. the octet offset status bits have no meaning until the fmstat bit is set to 1. an octet offset of 111 indicates byte alignment. an interrupt for recognition of the match character can be generated by setting the fril level to 1. since the matched character is the first byte written to the fifo, the frf interrupt occurs with the writing of the match character to the receive fifo. the operation of the receiver in transparent mode is summarized in table 44. table 44. receiver o p eration in trans p arent mode note: the match bit (fmatch) affects both the transmitter and the receiver. care should be taken to correctly program both the transm it idle character and the receive match character before setting fmatch. if the transmit idle character is programmed to ff (hex), the fmatch bit appears to affect only the receiver. faloct fmatch receiver operation x0 serial-to-parallel conversion begins with first rfdlck after fre, register fdl_pr1 bit 2, is set. data loaded to receive fifo immediately. 01 match user-defined character using sliding window. byte aligns once character is recognized. no data to receive fifo until match is detected. 11 match user-defined character, but only on octet boundary. boundary based on first rfdlck after fre, register fdl_pr1 bit 2, set. no data to receive fifo until match is detected. lucent technologies inc. 95 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. facility data link (continued) diagnostic modes loopbacks the serial link interface can operate in two diagnostic loopback modes: (1) local loopback and (2) remote loopback. the local loopback mode is selected when register fdl_pr1 bit 1 (fllb) is set to 1. the remote loopback is selected when register fdl_pr1 bit 0 (frlb) is set to 1. for normal traffic, i.e., to operate the transmitter and receiver independently, the fllp bit and the frlb bits should both be cleared to 0. local and remote loopbacks cannot be enabled simultaneously. in the local loopback mode: n tfdlck clocks both the transmitter and the receiver. n the transmitter and receiver must both be enabled. n the transmitter output is internally connected to the receiver input. n the tfdl is active. n the rfdl input is ignored. n the communication between the transmit and receive fifo buffers and the microprocessor continues normally. 5-4562(f)r.2 figure 34. local loopback mode in the remote loopback mode: n transmitted data is retimed with a maximum delay of 2 bits. n received data is retransmitted on the tfdl. the transmitter should be disabled. the receiver can be disabled or, if desired, enabled. received data is sent as usual to the receive fifo if the receiver is enabled xmit hdlc fdl block xmit hdlc fdl xmit interface xmit fifo rcvr fifo rcvr hdlc fdl rcvr interface tfdl tfdlck rfdlck rfdl rcvr hdlc fdl block 96 lucent technologies inc. preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 lucent technologies inc. facility data link (continued) 5-4563(f)r.1 figure 35. remote loopback mode xmit hdlc fdl block xmit hdlc fdl xmit interface xmit fifo rcvr fifo rcvr hdlc fdl rcvr interface tfdl tfdlck rfdlck rfdl rcvr hdlc fdl block phase-lock loop circuit the TFRA08C13 allows for independent transmit path and receive path clocking. the device provides outputs to control variable clock oscillators on both the transmit and receive paths. as such, the system may have both the transmit and receive paths phase-locked to two autonomous clock sources. the block diagram of the TFRA08C13 phase detector circuitry is shown in figure 36. the TFRA08C13 uses elastic store buffers (two frames) to accommodate the transfer of data from the system interface clock rate of 2.048 mbits/s to the line interface clock rate of either 1.544 mbits/s or 2.048 mbits/s. the transmit line side of the TFRA08C13 does not have any mechanism to monitor data overruns or underruns (slips) in its elastic store buffer. this interface relies on the requirement that the pllck clock signal (variable) is phase-locked to the chick clock signal (reference). when this requirement is not met, uncontrolled slips may occur in the transmit elastic store buffer that would result in cor- rupting data and no indication will be given. typically, a variable clock oscillator (vcxo) is used to drive the pllck signal. the TFRA08C13 provides a phase error signal (pllck-epll) that can be used to control the vcxo pllck. the pllck-epll signal is generated by monitoring the divided-down pllck (div-pllck) and chick (div-chick) signals. the div-chick sig- nal is used as the reference to determine the phase dif- ference between div-chick and div-pllck. while div-chick and divpllck are phase-locked, the pllck-epll signal is in a high-impedance state. a phase difference between div-chick and div-pllck drives pllck-epll to either 3.3 v or 0 v. an appropri- ate loop filter, for example, an rc circuit with r = 1 k w and c = 0.1 f, is used to filter these pllck-epll pulses to control the vcxo. the system can force chick to be phase-locked to rlck by using rlck as a reference signal to control a vcxo that is sourcing the chick signal. the TFRA08C13 uses the receive line signal (rlck) as the reference and the chick signal as the variable signal. the TFRA08C13 provides a phase error signal (chick-epll) that can be used to control the vcxo generating chick. the chick-epll signal is gener- ated by monitoring the divided-down chick signal (div-chick) and rlck (div-rlck) signals. the div- rlck signal is used as the reference to determine the phase difference between div-chick and div-rlck. while div-rlck and div-chick are phase-locked, the chick-epll signal is in a high-impedance state. a phase difference between div-rlck and div-chick drives chick-epll to either 3.3 v or 0 v. an appropri- ate loop filter, for example, an rc circuit with r = 1 k w and c = 0.1 f, is used to filter these chick-epll pulses to control the vcxo. in this mode, the TFRA08C13 can be programmed to act as a master timing source and is capable of generating the system frame synchronization signal through the chifs pin and setting frm_pr45 bit 4 to 1. lucent technologies inc. 97 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. phase-lock loop circuit (continued) 5-5268(f).a figure 36. TFRA08C13 phase detector circuitry tpd, tnd tlck transmit framer receive concentration highway interface rchidata chick chifs transmit concentration highway interface receive 2-frame elastic store buffer receive framer rpd, rnd rlck read address transmit 2-frame elastic store buffer pllck divider circuit internal_xlck pllck div-pllck digital phase detector chick divider circuit pllck-epll div-chick voltage- controlled crystal oscillator (vcxo) chick tchidata chifs system data write address system data read address facility data write address facility data slip monitor buffer overrun buffer underrun rlck divider circuit digital phase detector chick divider circuit div-rlck div-chick chick_epll voltage- controlled crystal oscillator (vcxo) internal_chick internal_rlck internal_chick external circuit external circuit preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 98 lucent technologies inc. lucent technologies inc. framer-system interface ds1 modes the ds1 framing formats require rate adaptation from the 1.544 mbits/s line interface bit stream to the system interface which functions at multiples of a 2.048 mbits/s bit stream. the rate adaptation results in the need for eight stuffed time slots on the system interface since there are only 24 ds1 (1.544 mbits/s) payload time slots while there are 32 system (2.048 mbits/s) time slots. placement of the stuffed time slots is defined by register frm_pr43 bit 0bit 2. cept modes the framer maps the line time slots into the corre- sponding system time slot one-to-one. framing time slot 0, the fas and nfas bytes, are placed in system time slot 0. receive elastic store the receive interface between the framer and the sys- tem chi includes a 2-frame elastic store buffer to enable rate adaptation. the receive line elastic store buffer contains circuitry that monitors the read and write pointers for potential data overrun and underrun (slips) conditions. whenever this slip circuitry deter- mines that a slip may occur in the receive elastic store buffer, it will adjust the read pointer such that a con- trolled slip is performed. the controlled slip is imple- mented by dropping or repeating a complete frame at the frame boundaries. the occurrence of controlled slips in the receive elastic store are indicated in the sta- tus register frm_sr3 bit 6 and bit 7. transmit elastic store the transmit interface between the framer and the sys- tem chi includes a 2-frame elastic store buffer to enable rate adaptation. the line transmit clock applied to pllck[18] must be phase-locked to chick. no indication of a slip in the transmit elastic store is given. concentration highway interface each framer has a dual, high-speed, serial interface to the system known as the chi. this flexible bus archi- tecture allows the user to directly interface to other lucent components which use this interface, as well as to mitel* and amd ? tdm highway interfaces, with no glue logic. configured via the highway control registers frm_pr45 through frm_pr66, this interface can be set up in a number of different configurations. the following is a list of the chi features: n lucent technologies standard interface for communi- cation devices. n two pairs of transmit and receive paths to carry data in 8-bit time slots. n programmable definition of highways through offset and clock-edge options which are independent for transmit and receive directions. n programmable idle code substitution of received time slots. n programmable 3-state control of each transmit time slot. n independent transmit and receive framing signals to synchronize each direction of data flow. n an 8 khz frame synchronization signal internally generated from the received line clock. n compatible with mitel and amd pcm highways. supported is the optional configuration of the chi which presents the signaling information along with the data in any framing modes when the device is pro- grammed for the associated signaling mode (asm). this mode is discussed in the signaling section. data can be transmitted or received on either one of two interface ports, called chidata and chidatab. the user-supplied clock (chiclk) controls the timing on the transmit or receive paths. individual time slots are referenced to the frame synchronization (chifs) pulse. each frame consists of 32 time slots at a pro- grammable data rate of 2.048 mbits/s, 4.096 mbits/s, or 8.192 mbits/s requiring a clock (chick) of the same rate. the clock and data rates of the transmit and receive highways are programmed independently. * mitel is a registered trademark of mitel corporation. ? amd is a registered trademark of advanced micro devices, inc. lucent technologies inc. 99 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. concentration highway interface (continued) rate adaptation is required for all ds1 formats between the 1.544 mbits/s line rate and 2.048 mbits/s, 4.966 mbits/s, or 8.182 mbits/s chi rate. this is achieved by means of stuffing eight idle time slots into the existing twenty-four time slots of the t1 frame. idle time slots can occur every fourth time slot (starting in the first, second, third, or fourth time slot) or be grouped together at the end of the chi frame as described in register frm_pr43 bit 0bit 2. the posi- tioning of the idle time slots is the same for transmit and receive directions. idle time slots contain the pro- grammable code of register frm_pr23. unused time slots can be disabled by forcing the tchidata inter- face to a high-impedance state for the interval of the disabled time slots. chi parameters the chi parameters that define the receive and transmit paths are given in table 45. table 45. summary of the TFRA08C13s concentration highway interface parameters name description hwyen highway enable (frm_pr45 bit 7). a 1 in this bit enables the transmit and receive concentration highway interfaces. this allows the framer to be fully configured before transmission to the highway. a 0 forces the idle code as defined in register frm_pr22, to be transmitted to the line in all payload time slots while tchidata is forced to a high-impedance state for all chi transmitted time slots. chimm concentration highway master mode (prm_pr45 bit 4). the default mode chimm = 0 enables an external system frame synchronization signal (chifs) to drive the transmit chi. a 1 enables the transmit chi to generate a system frame syn- chronization signal from the receive line clock. the transmit chi system frame syn- chronization signal is generated on the chifs output pin. applications using the receive line clock as the reference clock signal of the system are recommended to enable this mode and use the chifs signal generated by the framer. the receive chi path is not affected by this mode. chidts chi double time-slot mode (frm_pr65 bit 1 and frm_pr66 bit 1). chidts defines the 4.096 mbits/s and 8.192 mbits/s chi modes. chidts = 0 enables the 32 contiguous time-slot mode. this is the default mode. chidts = 1 enables the double time-slot mode in which the transmit chi drives tchidata for one time slot and then 3-states for the subsequent time slot, and the receive chi latches data from rchi- data for one time slot and then ignores the following time slot and so on. chidts = 1 allows two chis to interleave frames on a common bus. tfe transmit frame ed g e ( frm_pr46 bit 3 ) . tfe = 0 ( or 1 ) , chifs is sampled on the fallin g ( or risin g) ed g e of chick. in chimm ( chi master mode ) , the chifs pin outputs a transmit frame strobe to provide s y nchronization for tchidata. when tfe = 1 ( or 0 ) , chifs is centered around risin g ( or fallin g) ed g e of chick. in this mode, chifs can be used for receive data on rchidata. the timin g for chifs in chimm = 1 mode is identical to the timin g for chifs in chimm = 0 mode. rfe receive frame ed g e ( frm_pr46 bit 7 ) . rfe = 0 ( or 1 ) , chifs is sampled on the fallin g ( or risin g) ed g e of chick. cdrs0cdrs1 chi data rate ( frm_pr45 bit 2 and bit 3 ) . two-bit control for selectin g the chi data rate. the default state ( 00 ) enables the 2.048 mbits/s. cdrs bit: 2 3 chi data rate 0 0 2.048 mbits/s 0 1 4.096 mbits/s 1 0 8.192 mbits/s 1 1 reserved preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 100 lucent technologies inc. lucent technologies inc. name description tce transmitter clock edge (frm_pr47 bit 6) . tce = 0 (or 1), tchidata is clocked on the falling (or rising) edge of chick. rce receiver clock edge (frm_pr48 bit 6) . rce = 0 (or 1), rchidata is latched on the falling (or rising) edge of chick. ttse31ttse0 transmit time-slot enable 310 (frm_pr49frm_pr52). these bits define which transmit chi time slots are enabled. a 1 enables the tchidata or tchidatab time slot. a 0 forces the chi transmit highway time slot to be 3-stated. rtse31rtse0 receive time-slot enable 310 (frm_pr53frm_pr56). these bits define which receive chi time slots are enabled. a 1 enables the rchidata or rchdatab time slots. a 0 disables the time slot and transmits the programmable idle code of reg- ister frm_pr22 to the line interface. ths31ths0 transmit highway select 310 (frm_pr57frm_pr60). these bits define which transmit chi highway, tchidata or tchidatab, contains valid data for the active time slot. a 0 enables tchidata; a 1 enables the tchidatab. rhs31rhs0 receive highway select 310 (frm_pr61frm_pr64). these bits define which receive chi highway, rchidata or rchidatab, contains valid data for the active time slot. a 0 enables rchidata; a 1 enables the rchidatab. toff2toff0 transmitter bit offset (frm_pr46 bit 0bit 2) . these bits are used in conjunction with the transmitter byte offset to define the beginning of the transmit frame. they determine the offset relative to tchifs, for the first bit of transmit time slot 0. the off- set is the number of chick cycles by which the first bit is delayed. roff2roff0 receiver bit offset (frm_pr46 bit 4bit 6) . these bits are used in conjunction with the receiver byte offset to define the beginning of the receiver frame. they deter- mine the offset relative to the rchifs, for the first bit of receive time slot 0. the offset is the number of chick cycles by which the first bit is delayed. tbyoff6tbyoff0 transmitter byte offset (frm_pr47 bit 0bit 5 and frm_pr65 bit 0) . these bits determine the offset from the chifs to the beginning of the next frame on the trans- mit highway. note that in the asm mode, a frame consists of 64 contiguous bytes; whereas in other modes, a frame contains 32 contiguous bytes. allowable offsets: 2.048 mbits/s 031 bytes. 4.096 mbits/s 063 bytes. 8.192 mbits/s 0127 bytes. rbyoff6rbyoff0 receiver byte offset (frm_pr48 bit 0bit 5 and frm_pr66 bit 0) . these bits determine the offset from chifs to the beginning of the receive chi frame. note that in the asm mode, a frame consists of 64 contiguous bytes; whereas in other modes, a frame contains 32 contiguous bytes. allowable offsets: 2.048 mbits/s 031 bytes. 4.096 mbits/s 063 bytes. 8.192 mbits/s 0127 bytes. asm associated signaling mode (frm_pr44 bit 2) . when enabled, the associate sig- naling mode configures the chi to carry both payload data and its associated signal- ing information. enabling this mode must be in conjunction with the programming of the chi data rate to either 4.048 mbits/s or 8.096 mbits/s. each time slot consists of 16 bits where 8 bits are data and the remaining 8 bits are signaling information. sts0sts2 stuffed time slots (frm_pr43 bit 0bit 2). valid only in t1 framing formats, these 3 bits define the location of the eight stuffed chi (unused) time slots. concentration highway interface (continued) table 45. summary of the TFRA08C13s concentration highway interface parameters (continued) lucent technologies inc. 101 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. concentration highway interface (continued) chi frame timing chi timing with chidts disabled figure 37 illustrates the chi frame timing when chidts is disabled (registers frm_pr65 bit 1 (tchidts) and frm_pr66 bit 1 (rchdts) = 0) and the chi is not in the associated signaling mode (frm_pr44 bit 2 (asm) = 0). the frames are 125 ms long and consist of 32 contiguous time slots. in ds1 frame modes, the chi frame consists of 24 payload time slots and eight stuffed (unused) time slots. in cept frame modes, the chi frame consists of 32 payload time slots. 5-5269(f).ar.2 * the position of the stuffed time is controlled by register frm_pr43 bit 0bit 2. figure 37. nominal concentration highway interface timing (for frm_pr43 bit 0bit 2 = 100 (binary)) chifs 125 m s tchidata frame 1 frame 1 frame 2 rchidata frame 2 8.192 mbits/s chi: frame 1 frame 2 rchidata 4.096 mbits/s chi: 2.048 mbits/s chi: tchidata frame 1 frame 2 high impedance high impedance 24 valid time slots high impedance frame 2 tchidata frame 2 rchidata ds1 format frame 1 frame 2 2.048 mbits/s chi: rchidata tchidata or cept format 32 valid time slots 24 valid time slots 8 stuffed slots* frame 1 preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 102 lucent technologies inc. lucent technologies inc. concentration highway interface (continued) chi timing with chidts enabled figure 38 illustrates the chi frame timing when chidts is enabled (registers frm_pr65 bit 1 (tchidts) and frm_pr66 bit 1 (rchidts) = 1) and asm is disabled (register frm_pr44 bit 2 (asm) = 0). in the chidts mode, valid chi payload time slots are alternated with high-impedance intervals of one time-slot duration. this mode is valid only for 4.096 mbits/s and 8.192 mbits/s chi rates. 5-6454(f)r.3 figure 38. chidts mode concentration highway interface timing chifs 125 m s tchidata ts0 rchidata 8.192 mbits/s chi rchidata 4.096 mbits/s chi tchidata high impedance ts1 ts2 ts3 ts0 ts1 ts2 ts3 ts31 ts0 ts31 ts0 frame 1 time slot 8 bits time slot frame 2 ts0 ts1 ts31 ts31 ts0 ts0 ts1 ts0 ts4 ts30 ts4 t30 ts2 ts30 ts2 ts30 lucent technologies inc. 103 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. concentration highway interface (continued) chi timing with associated signaling mode enabled figure 39 illustrates the chi frame timing when the associated signaling mode is enabled (register frm_pr44 bit 2 (asm) = 1) and the chidts mode is disabled (registers frm_pr65 bit 1 (tchidts) = 0 and frm_pr66 bit 1 (rchidts) = 0). the frames are 125 ms long and consist of 32 contiguous 16-bit time slots. in ds1 frame formats, each frame consists of 24 time slots and eight stuffed time slots. each time slot consists of two octets. in cept modes, each frame consists of 32 time slots. each time slot consists of two octets. 5-5270(f).ar.3 figure 39. associated signaling mode concentration highway interface timing chi timing with associated signaling mode and chidts enabled figure 40 illustrates the chi frame timing in the associated signaling mode (register frm_pr44 bit 2 (asm) = 1) and chidts enabled (registers frm_pr65 bit 1 (tchidts) = 1 and frm_pr66 bit 1 (rchidts) = 1). 5-6454(f).ar.2 * high-impedance state for tchidata and not received (dont care) for rchidata. figure 40. chi timing with asm and chidts enabled chifs 125 m s frame 1 frame 2 8.192 mbits/s chi: rchidata 4.096 mbits/s chi: tchidata frame 1 frame 1 frame 2 frame 2 high impedance rchidata tchidata or frame = 64 bytes: 32 data + 32 signaling data and signaling bytes are interleaved signaling 0 data 0 signaling 31 data 0 data 31 frame data signaling ts0 ts1 ts31 ts0 16 bits 1 time slot 16 bits 1 time slot 8.192 mbits/s chi with asm (associated signaling mode) enabled data signaling tchidata or rchidata * * * preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 104 lucent technologies inc. lucent technologies inc. * the orca series 3 fpga data sheet contains more information on how to control these signals during start-up. the timing of done release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all user i/os) is controlled by a second set of options. concentration highway interface (continued) chi offset programming to facilitate bit offset programming, two additional internal parameters are introduced: cex is defined as the clock edge with which the first bit of time slot 0 is transmitted; cer is defined as the clock edge on which bit 0 of time slot 0 is latched. cex and cer are counted relative to the edge on which the chifs signal is sampled. values of cex and cer depend upon the values of the parameters described above. the following table gives decimal values of cex and cer for various values of tfe, rfe, tce, rce, toff[2:0], and roff[2:0]. the byte (time slot) offsets are assumed to be zero in the following examples. table 46. programming values for toff[2:0] and roff[2:0] when cms = 0 figure 41 shows an example of the relative timing of chi 2.048 mbits/s data with the following parameters: n cms = 0, tfe, rfe = 0. n tce = 1, toff[2:0] = 000, tbyoff[6:0] = 0000000. n rce = 0, roff[2:0] = 000, rbyoff[6:0] = 0000000. 5-2202(f).d figure 41. tchidata and rchidata to chick relationship with cms = 0 (cex = 3 and cer = 4, respectively) rfe/ tfe rce/ tce roff[2:0] or toff[2:0] 000 001 010 011 100 101 110 111 cer or cex (decimal) 00 4681012141618 0 1 3 5 7 9 11 13 15 17 1 0 3 5 7 9 11 13 15 17 11 4681012141618 chifs is sampled on this edge: fe = 0 1 2 3 4 5 6 7 8 bit 0, ts 0 bit 1, ts 0 bit 2, ts 0 cex = 3 cer = 4 bit 0, ts 0 bit 1, ts 0 bit 2, ts 0 high impedance rchidata: rce = 0 tchidata: tce = 1 chifs chick lucent technologies inc. 105 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. concentration highway interface (continued) figure 42 and figure 43 illustrate the chi timing. 5-3916(f).d note: for case illustrated, rfe = 0, and rce = 0. figure 42. receive chi (rchidata) timing 5-3917(f).d note: for case illustrated, tfe = 0 and tce = 0. figure 43. transmit chi (tchidata) timing chiclk chifs rchidata t14s t14h t14s: chifs setup = 30 ns min t15h t14h: chifs hold = 45 ns min t15s: rchidata setup = 25 ns min t15s t15s: rchidata hold = 25 ns min chiclk chifs tchidata t14s t14h t14s: chifs setup = 35 ns min t19 t14h: chifs hold = 45 ns min t19: chick to tchidata delay = 25 ns max jtag boundary-scan specification principle of the boundary scan the boundary scan (bs) is a test aid for chip, module, and system testing. the key aspects of bs are as fol- lows: n testing the connections between ics on a particular board. n observation of signals to the ic pins during normal operating functions. n controlling the built-in-self-test (bist) of an ic. TFRA08C13 does not support bs-bist. designed according to the ieee std. 1149.1-1990 standard, the bs test logic consists of a defined interface: the test access port (tap). the tap is made up of four signal pins assigned solely for test purposes. the fifth test pin ensures that the test logic is initialized asynchronously. the bs test logic also comprises a 16- state tap controller, an instruction register with a decoder, and several test data registers (bs register, bypass register, and idcode register). the main component is the bs register that links all the chip pins to a shift register by means of special logic cells. the test logic is designed in such a way that it is operated independently of the application logic of the TFRA08C13 (the mode multiplexer of the bs output cells may be shared). figure 44 illustrates the block diagram of the TFRA08C13s bs test logic. preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 106 lucent technologies inc. lucent technologies inc. jtag boundary-scan specification (continued) 5-3923(f)r.4 figure 44. block diagram of the TFRA08C13's boundary-scan test logic boundary-scan register tdi trst tms tck tap controller instruction decoder out tdo in mux chip kernel (unaffected by boundary-scan test) idcode register bypass register instruction register lucent technologies inc. 107 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. jtag boundary-scan specification (continued) test access port controller the test access port controller is a synchronous sequence controller with 16 states. the state changes are preset by the tms, tck, and trst signals and by the previous state. the state changes always take place when the tck edge rises. figure 45 shows the tap controller state diagram. 5-3924(f)r.5 figure 45. bs tap controller state diagram the value shown next to each state transition in figure 45 represents the signal present at tms at the time of a ris- ing edge at tck. the description of the tap controller states is given in ieee std. 1149.1-1990 section 5.1.2 and is reproduced in table 49 and table 50. select-dr capture-dr 1 0 0 1 1 shift-dr exit1-dr pause-dr 0 1 exit2-dr update-dr 1 10 0 0 0 test logic reset run test/ idle 1 0 select-ir capture-ir 1 0 0 1 1 shift-ir exit1-ir pau s e - i r 0 1 exit2-ir update-ir 1 10 0 0 0 trst = 0 0 1 1 preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 108 lucent technologies inc. lucent technologies inc. jtag boundary-scan specification (continued) table 47. tap controller states in the data register branch table 48. tap controller states in the instruction register branch name description test logic reset the bs logic is switched in such a way that normal operation of the asic is adjusted. the idcode instruction is initialized by test logic reset. irre- spective of the initial state, the tap controller has achieved test logic reset after five control pulses at the latest when tms = 1. the tap controller then remains in this state. this state is also achieved when trst = 0. run test/idle using the appropriate instructions, this state can activate circuit parts or initiate a test. all of the registers remain in their present state if other instructions are used. select-dr this state is used for branching to the test data register control. capture-dr the test data is loaded in the test data register parallel to the rising edge of tck in this state. shift-dr the test data is clocked by the test data register serially to the rising edge of tck in the state. the tdo output driver is active. exit(1/2)-dr this temporary state causes a branch to a subsequent state. pause-dr the input and output of test data can be interrupted in this state. update-dr the test data is clocked into the second stage of the test data register parallel to the falling edge of tck in this state. name description select-ir this state is used for branching to the instruction register control. capture-ir the instruction code 0001 is loaded in the first stage of the instruction register parallel to the rising edge of tck in this state. shift-ir the instructions are clocked into the instruction register serially to the rising edge of tck in the state. the tdo output driver is active. exit(1/2)-ir this temporary state causes a branch to a subsequent state. pause-ir the input and output of instructions can be interrupted in this state. update-ir the instruction is clocked into the second stage of the instruction register parallel to the falling edge of tck in this state. lucent technologies inc. 109 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. jtag boundary-scan specification (continued) instruction register the instruction register (ir) is 4 bits in length. table 49 shows the bs instructions implemented by the TFRA08C13. table 49. TFRA08C13s boundary-scan instructions instruction code act. register tdi ? tdo mode function output defined via extest 0000 boundary scan test test external connections bs register idcode 0001 identification normal read manuf. register core logic highz 0100 bypass x 3-state outputhigh impedance sample/preload 0101 boundary scan normal sample/load core logic bypass 1111 bypass normal min. shift path core logic everything else bypass x outputhigh impedance the instructions not supported in TFRA08C13 are intest, runbist, toggle. a fixed binary 0001 pat- tern (the 1 into the least significant bit) is loaded into the ir in the capture-ir controller state. the idcode instruction (binary 0001) is loaded into the ir during the test-logic-reset controller state and at powerup. the following is an explanation of the instructions sup- ported by TFRA08C13 and their effect on the devices' pins. extest this instruction enables the path cells, the pins of the ics, and the connections between asics to be tested via the circuit board. the test data can be loaded in the chosen position of the bs register by means of the sample/preload instruction. the extest instruc- tion selects the bs register as the test data register. the data at the function inputs is clocked into the bs register on the rising edge of tck in the capture-dr state. the contents of the bs register can be clocked out via tdo in the shift-dr state. the value of the function outputs is solely determined by the contents of the data clocked into the bs register and only changes in the update-dr state on the falling edge of tck. dcode information regarding the manufacturers id for lucent, the ic number, and the version number can be read out serially by means of the idcode instruction. the idcode register is selected, and the bs register is set to normal mode in the update-ir state. the idcode is loaded at the rising edge of tck in the capture- dr state. the idcode register is read out via tdo in the shift-dr state. highz all 3-statable outputs are forced to a high-impedance state, and all bidirectional ports to an input state by means of the highz instruction. the impedance of the outputs is set to high in the update-ir state. the func- tion outputs are only determined in accordance with another instruction if a different instruction becomes active in the update-ir state. the bypass register is selected as the test data register. the highz instruc- tion is implemented in a similar manner to that used for the bypass instruction. sample/preload the sample/preload instruction enables all the input and output pins to be sampled during operation (sample) and the result to be output via the shift chain. this instruction does not impair the internal logic functions. defined values can be serially loaded in the bs cells via tdi while the data is being output (pre- load). preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 110 lucent technologies inc. lucent technologies inc. jtag boundary-scan specification (continued) bypass this instruction selects the bypass register. a minimal shift path exists between tdi and tdo. the bypass reg- ister is selected after the update-ir. the bs register is in normal mode. a 0 is clocked into the bypass register during capture-dr state. data can be shifted by the bypass register during shift-dr. the contents of the bs register do not change in the update-dr state. please note that a 0 that was loaded during capture-dr appears first when the data is being read out. boundary-scan register the boundary-scan register is a shift register, whereby one or more bs cells are assigned to every digital TFRA08C13 pin (with the exception of the pins for the bs architecture, analog signals, and supply voltages). the TFRA08C13s boundary-scan register bit-to-pin assignment is defined in the bsdl file, which is available upon request. please call 1-800-teckfax (1-800-832-5329). bypass register the bypass register is a one-stage shift register that enables the shift chain to be reduced to one stage in the TFRA08C13. dcode register the idcode register identifies the TFRA08C13 by means of a parallel, loadable, 32-bit shift register. the code is loaded on the rising edge of tck in the capture-dr state. the 32-bit data is organized into four sections as fol- lows. table 50. idcode register 3-state procedures the 3-state input participates in the boundary scan. it has a bs cell, but buffer blocking via this input is suppressed for the extest instruction. the 3-state input is regarded as a signal input that is to participate in the connection test during extest. the buffer blocking function should not be active during extest to ensure that the update pattern at the TFRA08C13 outputs does not become corrupted. version part number manufacturer id 1 bits 3128 bits 2712 bits 111 bit 0 0001 0111011000110100 00000011101 1 lucent technologies inc. 111 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. microprocessor interface overview the TFRA08C13 device is equipped with a micropro- cessor interface that can operate with most commer- cially available microprocessors. the microprocessor interface provides access to all the internal registers through a 12-bit address bus and an 8-bit data bus. input mpmode (pin af9) is used to configure this interface into one of two possible modes, as shown in table 51. the mpmode setting selects the associated set of control signals required to access a set of regis- ters within the device. the microprocessor interface can operate at speeds up to 33 mhz in interrupt-driven or polled mode without requiring any wait-states. for microprocessors operat- ing at greater than 33 mhz, the rdy_dtack output (pin v26) may be used to introduce wait-states in the read/write cycles. in the interrupt-driven mode, one or more device alarms will assert the interrupt output (pin ad9) once per alarm activation. after the microprocessor identifies the source(s) of the alarm(s) (by reading the global interrupt register) and reads the specific alarm status registers, the interrupt output will deassert. in the polled mode, however, the microprocessor moni- tors the various device alarm status by periodically reading the alarm status registers within the TFRA08C13 without the use of interrupt. in both interrupt and polled methods of alarm servicing, the status registers within an identified block will clear on a microprocessor read cycle only when the alarm condi- tion within that block no longer exists; otherwise, the alarm status register bit remains set. the powerup default states for the line interface unit, framer, and the hdlc blocks are discussed in their respective sections. all read/write registers within these blocks must be written by the microprocessor on system start-up to guarantee proper device functional- ity. register addresses not defined in this data sheet must not be written. details concerning the microprocessor interface con- figuration modes, pinout definitions, clock specifica- tions, register address map, i/o timing specifications, and the i/o timing diagrams are described in the follow- ing sections. microprocessor configuration modes table 51 highlights the two microprocessor modes controlled by the mpmode input (pin af9) table 51 . micro p rocessor confi g uration modes * the dtack signal is asynchronous to the mpclk signal. mode mpmode generic control, data, and output pin names mode 1 0 cs , as , ds , r/ w , a [ 11:0 ] , d [ 7:0 ] , interrupt, dtack * mode 3 1 cs , ale , rd , wr , a [ 11:0 ] , d [ 7:0 ] , interrupt, rdy preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 112 lucent technologies inc. lucent technologies inc. microprocessor interface (continued) microprocessor interface pinout definitions the mode [1 and 3] specific pin definitions are given in table 52. note that the microprocessor interface uses the same set of pins in all modes. table 52. mode [1 and 3] micro p rocessor pin definitions 1. interrupt output is synchronous to the internal clock source rlck-liu. if rlck_liu is absent, the reference clock for interr upt timing becomes an interval 2.048 mhz clock derived from the chi clock. 2. in the default (reset) mode, interrupt is active-high. it can be made active-low by setting register greg4 bit 6 to 1. 3. the dtack output is asynchronous to mpclk. 4. see table 2. pin descriptions. 5. mpclk is needed if rdy output is required to be synchronous to mpclk. microprocessor clock (mpclk) specifications the microprocessor interface is designed to operate at clock speeds up to 16 mhz without requiring any wait- states. wait-states may be needed if higher microprocessor clock speeds are required. the microprocessor clock (mpclk, pin ae10) specification is shown in table 53. this clock must be supplied only if the rdy (mode 3) is required to be synchronous to mpclk. table 53. micro p rocessor in p ut clock s p ecifications configuration pin number device pin name generic pin name pin_type assertion sense function mode 1 v24 wr _ds ds input active-low data strobe u26 rd _r/w r/w input read/write r/w = 1 => read r/w = 0 => write u23 ale_as as input active-low address strobe u25 cs cs input active-low chip select ad9 interrupt interrupt 1 output active-high/ low 2 interrupt v26 rdy_dtack dtack 3 output active-low data acknowledge note 4 d[7:0] d[7:0] i/o data bus note 4 a[11:0] a[11:0] input address bus ae10 mpclk mpclk input microprocessor clock mode 3 v24 wr _ds wr input active-low write u26 rd _r/w rd input active-low read u23 ale _as ale input active-low address latch enable u25 cs cs input active-low chip select ad9 interrupt interrupt 1 output active-high/ low interrupt v26 rdy_dtack rdy 5 output active-high ready note 4 d[7:0] d[7:0] i/o data bus note 4 a[11:0] a[11:0] input address bus ae10 mpclk mpclk input microprocessor clock name symbol period and toler ance t rise typ t fall typ duty cycle unit min high min low mpclk t1 30 to 323 2 2 12 12 ns lucent technologies inc. 113 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. microprocessor interface (continued) microprocessor interface register address map the register address space is divided into thirteen (13) contiguous banks of 512 addressable units each. each addressable unit is an 8-bit register. these register banks are labeled as regbank[012]. the register address map table gives the address range of these register banks and their associated circuit blocks. regbank0 contains the global registers which are common to all the circuit blocks on the TFRA08C13. regbank[18] are attached to the framer circuit blocks. regbank[912] are attached to the fdl circuit blocks. the descriptions of the indi- vidual register banks can be found in the appropriate sections of this document. in these descriptions, all addresses are given in hexadecimal. addresses out of the range specified by table 54 must not be addressed. if they are written, they must be written to 0. an inadvertent write to an out-of-range address may be corrected by a device reset. table 54 . TFRA08C13 re g ister address ma p * core registers are common to all circuit blocks on the TFRA08C13. i/o timing * the i/o timing specifications for the microprocessor interface are given in table 55. the microprocessor interface pins are compatible with cmos/ttl i/o levels. all outputs, except the data bus d[7:0], are rated for a capacitive load of 50 pf. the d[7:0] outputs are rated for a 100 pf load. * see product advisory ay99-041 for more information. register bank label start address (in hex) end address (in hex) circuit block name regbank0 000 008 octal global re g isters * regbank1 200 2e0 2a6 2ff framer1 regbank2 300 3e0 3a6 3ff framer2 regbank3 400 4e0 4a6 4ff framer3 regbank4 500 5e0 5a6 5ff framer4 regbank5 600 6e0 6a6 6ff framer5 regbank6 700 7e0 7a6 7ff framer6 regbank7 800 8e0 8a6 8ff framer7 regbank8 900 9e0 9a6 9ff framer8 regbank9 a00 a20 a0e a2f facilit y data link 1 ( fdl1 ) facilit y data link 2 ( fdl2 ) regbank10 b00 b20 b0e b2f facilit y data link 3 ( fdl3 ) facilit y data link 4 ( fdl4 ) regbank11 c00 c20 c0e c2f facilit y data link 5 ( fdl5 ) facilit y data link 6 ( fdl6 ) regbank12 d00 d20 d0e d2f facilit y data link 7 ( fdl7 ) facilit y data link 8 ( fdl8 ) preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 114 lucent technologies inc. lucent technologies inc. microprocessor interface (continued) table 55. micro p rocessor interface i/o timin g s p ecifications note: the read and write timing diagrams for all four microprocessor interface modes are shown in figure 46figure 49. symbol configuration parameter setup (ns) (min) hold (ns) (min) delay (ns) (max) t1 mode 1 as asserted width 10 t2 address valid to as deasserted 10 t3 as deasserted to address invalid 10 t4 t5 r/w valid to both cs and ds asserted 40 t6 address valid and as asserted to ds asserted (read) 5 t7 cs asserted to dtack low impedance 12 t8 ds asserted to dtack asserted 15 t9 ds asserted to ad low impedance (read) 19 t10 dtack asserted to data valid 25 t11 ds deasserted to cs deasserted (read) 8 t12 ds deasserted to r/w invalid 5 t13 ds deasserted to dtack deasserted 12 t14 cs deasserted to dtack high impedance 10 t15 ds deasserted to data invalid (read) 5 t16 address valid and as asserted to ds asserted (write) 10 t17 data valid to ds asserted 10 t18 ds deasserted to cs deasserted (write) 8 t19 ds deasserted to data valid 10 t20 ds asserted width (write) 10 t21 t22 t23 t24 t25 cs asserted to ds asserted (write) 10 lucent technologies inc. 115 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. microprocessor interface (continued) table 55. micro p rocessor interface i/o timin g s p ecifications ( continued ) note: the read and write timing diagrams for all four microprocessor interface modes are shown in figure 46figure 49. symbol configuration parameter setup (ns) (min) hold (ns) (min) delay (ns) (max) t31 mode 3 ale asserted width 10 t32 address valid to ale deasserted 10 t33 ale deasserted to address invalid 10 t34 cs asserted to rd asserted 5 t35 address valid and ale asserted to rd asserted 5 t36 cs asserted to rdy low impedance 12 t37 rising edge mpck to rdy asserted 15 t38 rd asserted to ad low impedance 19 t39 rd asserted to data valid 40 t40 rd deasserted to cs deasserted 5 t41 rd deasserted to rdy deasserted 15 t42 cs deasserted to rdy high impedance 10 t43 rd deasserted to data invalid (high impedance) 5 t44 cs asserted to wr asserted 6 t45 address valid and ale asserted to wr asserted 10 t46 data valid to wr asserted 10 t47 wr deasserted to cs deasserted 7 t48 wr deasserted to rdy deasserted 15 t49 wr deasserted to data invalid 10 t50 rd asserted width 40 t51 wr asserted width 50 t52 t53 t54 t55 preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 116 lucent technologies inc. lucent technologies inc. microprocessor interface (continued) 5-6422(f).a figure 46. mode 1read cycle timing (mpmode = 0) 5-6423(f).a figure 47. mode 1write cycle timing (mpmode = 0) d[0:7] dtack ds r/w a[0:11] as cs t1 t2 t3 valid address t5 t6 t7 t8 t10 t9 valid data t13 t15 t14 t12 t11 d[0:7] dtack ds r/w a[0:11] as cs t1 t2 t3 valid address t16 t25 t7 t8 t17 valid data t13 t19 t14 t12 t18 t5 t20 lucent technologies inc. 117 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. microprocessor interface (continued) 5-6426(f).a figure 48. mode 3read cycle timing (mpmode = 1) 5-6427(f).a figure 49. mode 3write cycle timing (mpmode = 1) mpck d[0:7] rdy rd a[0:11] ale cs t31 t32 t33 valid address t34 t50 t35 valid data t42 t41 t37 t36 t40 t39 t38 t43 mpck d[0:7] rdy wr a[0:11] ale cs t31 t32 t33 valid address t44 t51 t45 valid data t42 t37 t36 t47 t46 t48 t49 preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 118 lucent technologies inc. lucent technologies inc. reset both hardware and software resets are provided. hardware reset (pin c19) hardware reset is enabled by asserting reset to 0. the device is in an inactive condition when reset is 0, and becomes active when reset is returned to 1. eight cycles of the liu receive line clock, i.e., 5.2 s for t1 or 3.9 s for e1, is required to guarantee a complete reset. hardware reset returns all framer and fdl registers to their default values, as listed in the individual register descriptions and register maps, (table 182table 186). hardware reset results in a complete device reset includ- ing a reset of the global registers. software reset/software restart independent software reset for each functional block of the device is available. the framer may be reset through register frm_pr26 bit 0 (swreset), or placed in restart through frm_pr26 bit 1 (swrestart). the fdl receiver may be reset through register fdl_pr26 bit 1 (frr), and the fdl transmitter may be reset through fdl_pr1 bit 5 (ftr). the reset functions, framer swreset (framer software reset), fdl frr (fdl receiver reset), and ftr (fdl transmitter reset), reset the block and return all parameter/control registers for the block to their default values. the restart function framer swrestart (framer software restart), resets the block but does not alter the value of the parameter/control registers. interrupt generation an interrupt may be generated by any of the conditions reported in the status registers. for a bit (condition) in a sta- tus register to create an interrupt, the corresponding interrupt enable bit must be set and the interrupt block enable in the global register for the source block must be set, see table 56 below. once the source interrupt register is read, the interrupt for that condition is deasserted. table 56. status register and corresponding interrupt enable register for functional blocks default for interrupt assertion is a logical 1 (high) value. but the assertion value and deasserted state is program- mable through register greg4 bit 4 and bit 6 and may take on the following state, see table 57 below. table 57. asserted value and deasserted state for greg4 bit 4 and bit 6 logic combinations functional block status register interrupt enable register primary block greg0 greg1 framer frm_sr0frm_sr7 frm_pr0frm_pr7 facility data link fdl_sr0 fdl_pr2 greg4 interrupt (pin ad-8) functionality bit 4 bit 6 asserted value deasserted value 0 0 high low 1 0 high 3-state wired-or 01 low high 1 1 low 3-state wired-and lucent technologies inc. 119 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. register architecture table 58 is an overview of the register architecture. the table is a summary of the register function and address. complete detail of each register is given in the following sections. table 58. register summary * the most significant digit, designated by y, is used to identify each framer (for framer 1framer 8, y = 29, respectively). register function register address (hex) * channel 18 global registers greg0 framer block interrupt status 000 greg1 framer block interrupt enable 001 greg2 fdl block interrupt status 002 greg3 fdl block interrupt enable 003 greg4 global control 004 greg5 device id and version 005 greg6 device id and version 006 greg7 device id and version 007 greg8 global control 008 greg9 global pllck control 009 framer registers status registers frm_sr0 interrupt status y00 frm_sr1 facility alarm condition y01 frm_sr2 remote end alarm y02 frm_sr3 facility errored event y03 frm_sr4 facility event y04 frm_sr5 exchange termination and exchange termination remote end interface status y05 frm_sr6 network termination and network termination remote end interface status y06 frm_sr7 facility event y07 frm_sr8, frm_sr9 bipolar violation counter y08, y09 frm_sr10, frm_sr11 framing bit error counter y0a, y0b frm_sr12, frm_sr13 crc error counter y0c, y0d frm_sr14, frm_sr15 e-bit counter y0e, y0f frm_sr16, frm_sr17 crc-4 error at nt1 from nt2 counter y10, y11 frm_sr18, frm_sr19 e-bit at nt1 from nt2 counter y12, y13 frm_sr20, frm_sr21 et errored seconds counter y14, y15 preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 120 lucent technologies inc. lucent technologies inc. register architecture (continued) table 58. register summary (continued) * the most significant digit, designated by y, is used to identify each framer (for framer 1framer 8, y = 29, respectively). register function register address (hex) * channel 18 framer registers (continued) status registers (continued) frm_sr22, frm_sr23 et bursty errored seconds counter y16, y17 frm_sr24, frm_sr25 et severely errored seconds counter y18, y19 frm_sr26, frm_sr27 et unavailable seconds counter y1a, y1b frm_sr28, frm_sr29 et-re errored seconds counter y1c, y1d frm_sr30, frm_sr31 et-re bursty errored seconds counter y1e, y1f frm_sr32, frm_sr33 et-re severely errored seconds counter y20, y21 frm_sr34, frm_sr35 et-re unavailable seconds counter y22, y23 frm_sr36, frm_sr37 nt1 errored seconds counter y24, y25 frm_sr38, frm_sr39 nt1 bursty errored seconds counter y26, y27 frm_sr40, frm_sr41 nt1 severely errored seconds counter y28, y29 frm_sr42, frm_sr43 nt1 unavailable seconds counter y2a, y2b frm_sr44, frm_sr45 nt1-re errored seconds counter y2c, y2d frm_sr46, frm_sr47 nt1-re bursty errored seconds counter y2e, y2f frm_sr48, frm_sr49 nt1-re severely errored seconds counter y30, y31 frm_sr50, frm_sr51 nt1-re unavailable seconds counter y32, y33 frm_sr52 receive not-fas ts0 y34 frm_sr53 received sa y35 frm_sr54 frm_sr63 slc -96 fdl/cept sa receive stack y36y3f received signaling registers frm_rsr0 frm_rsr31 received signaling y40y5f lucent technologies inc. 121 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. register architecture (continued) table 58. register summary (continued) * the most significant digit, designated by y, is used to identify each framer (for framer 1framer 8, y = 29, respectively). register function register address (hex) * channel 18 framer registers (continued) parameter/control registers frm_pr0 frm_pr7 interrupt group enable y60y67 frm_pr8 framer mode option y68 frm_pr9 framer crc control option y69 frm_pr10 alarm filter y6a frm_pr11 errored second threshold y6b frm_pr12, frm_pr13 severely errored second threshold y6c, y6d frm_pr14 errored event enable y6e frm_pr15 et remote end errored event enable y6f frm_pr16 nt1 errored event enable y70 frm_pr17, frm_pr18 nt1 remote end errored event enable y71, y72 frm_pr19 automatic ais to the system and automatic loopback enable y73 frm_pr20 transmit to the line command y74 frm_pr21 framer fdl loopback transmission codes command y75 frm_pr22 framer transmit line idle code y76 frm_pr23 framer transmit system idle code y77 frm_pr24 primary loopback control y78 frm_pr25 secondary loopback control y79 frm_pr26 system frame sync mask source y7a frm_pr27 transmission of remote frame alarm and cept automatic transmission of a bit = 1 control y7b frm_pr28 cept automatic transmission of e bit = 0 y7c frm_pr29 sa4sa8 source y7d frm_pr30 sa4sa8 control y7e frm_pr31 frm_pr40 sa transmit stack/ slc -96 transmit stack y7fy88 frm_pr41 si-bit source y89 frm_pr42 frame exercise y8a frm_pr43 system interface control y8b frm_pr44 signaling mode y8c frm_pr45 chi common control y8d frm_pr46 chi common control y8e frm_pr47 chi transmit control y8f frm_pr48 chi receive control y90 preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 122 lucent technologies inc. lucent technologies inc. register architecture (continued) table 58. register summary (continued) * the most significant digit, designated by y, is used to identify each framer (for framer 1framer 8, y = 29, respectively). ? for fdl 1 and fdl 2, y = a; for fdl 3 and fdl 4, y = b; for fdl 5 and fdl 6, y = c; for fdl 7 and fdl 8, y = d. register function register address (hex) * channel 18 framer registers (continued) parameter/control registers (continued) frm_pr49 frm_pr52 transmit chi time-slot enable y91y94 frm_pr53 frm_pr56 receive chi time-slot enable y95y98 frm_pr57 frm_pr60 chi transmit highway select y99y9c frm_pr61 frm_pr64 chi receive highway select y9dya0 frm_pr65 chi transmit control ya1 frm_pr66 chi receive control ya2 frm_pr69 auxiliary pattern generator control ya5 frm_pr70 auxiliary pattern detector control ya6 transmit signaling registers frm_tsr0 frm_tsr31 transmit signaling ye0yf7 facility data link registers fdl parameter/control registers register address (hex) ? fdl 1 fdl 3 fdl 5 fdl 7 fdl 2 fdl 4 fdl 6 fdl 8 fdl_pr0 fdl configuration control y00 y20 fdl_pr1 fdl control y01 y21 fdl_pr2 fdl interrupt mask control y02 y22 fdl_pr3 fdl transmitter configuration control y03 y23 fdl_pr4 fdl transmitter fifo y04 y24 fdl_pr5 fdl transmitter mask y05 y25 fdl_pr6 fdl receive interrupt level control y06 y26 fdl_pr7 not assigned fdl_pr8 fdl receive match character y08 y28 fdl_pr9 fdl transparent control y09 y29 fdl_pr10 fdl transmit ansi esf bit codes y0a y2a fdl status registers fdl_sr0 fdl interrupt status y0b y2b fdl_sr1 fdl transmitter status y0c y2c fdl_sr2 fdl receiver status y0d y2d fdl_sr3 fdl ansi bit codes status y0e y2e fdl_sr4 fdl receive fifo y07 y27 lucent technologies inc. 123 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. global register architecture regbank0 contains the status and programmable control registers for all global functions. the address of these registers is 000 (hex) to 009 (hex). these registers control the eight channels of the TFRA08C13. the register bank architecture is shown in table 59. the register bank consists of 8-bit registers classified as pri- mary block interrupt status register, primary block interrupt enable register, global loopback control register, global terminal control register, device identification register, and global internal interface control register. table 59. global register set (0x0000x009) * the following section describes the global registers intable 60table 67. global register structure framer block interrupt status register (greg0) a bit set to 1 indicates the block has recently generated an interrupt. this register is cleared on read. table 60. framer block interrupt status register (greg0) (000) global register address (hex) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 000 frmr8_i nt (0) frmr7_i nt (0) frmr6_i nt (0) frmr5_i nt (0) frmr4_i nt (0) frmr3_i nt (0) frmr2_i nt (0) frmr1_i nt (0) 001 frmr8ie (0) frmr7ie (0) frmr6ie (0) frmr5ie (0) frmr4ie (0) frmr3ie (0) frmr2ie (0) frmr1ie (0) 002 fdl8_int (0) fdl7_int (0) fdl6_int (0) fdl5_int (0) fdl4_int (0) fdl3_int (0) fdl2_int (0) fdl1_int (0) 003 fdl8ie (0) fdl7ie (0) fdl6ie (0) fdl5ie (0) fdl4e (0) fdl3ie (0) fdl2ie (0) fdl1ie (0) 004 reserved (0) ipc (0) reserved (0) itsc (0) reserved (0) secctrl 0 (0) secctrl 1 (0) secctrl 2 (0) 005 11111000 006 00000011 007 00000001 008 reserved (0) divmux0 (0) divmux1 (0) divmux2 (0) reserved (0) lomux0 (0) lomux1 (0) lomux2 (0) 009 eipllck8 (0) eipllck7 (0) eipllck6 (0) eipllck5 (0) eipllck4 (0) eipllck3 (0) eipllck2 (0) eipllck1 (0) bit symbol description 0 frmr1_int framer 1 interrupt. a 1 indicates framer 1 generated an interrupt. 1 frmr2_int framer 2 interrupt. a 1 indicates framer 2 generated an interrupt. 2 frmr3_int framer 3 interrupt. a 1 indicates framer 3 generated an interrupt. 3 frmr4_int framer 4 interrupt. a 1 indicates framer 4 generated an interrupt. 4 frmr5_int framer 5 interrupt. a 1 indicates framer 5 generated an interrupt. 5 frmr6_int framer 6 interrupt. a 1 indicates framer 6 generated an interrupt. 6 frmr7_int framer 7 interrupt. a 1 indicates framer 7 generated an interrupt. 7 frmr8_int framer 8 interrupt. a 1 indicates framer 8 generated an interrupt. preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 124 lucent technologies inc. lucent technologies inc. global register structure (continued) framer block interrupt enable register (greg1) this register enables the individual blocks to assert the interrupt pin high. table 61. framer block interrupt enable register (greg1) (001) fdl block interrupt status enable register (greg2) table 62. fdl block interrupt status register (greg2) (002) fdl block interrupt enable register (greg3) this register enables the individual blocks to assert the interrupt pin high. table 63. fdl block interrupt enable register (greg3) (003) bit symbol description 0 frmr1ie framer 1 interrupt enable. a 1 enables framer 1 interrupts. 1 frmr2ie framer 2 interrupt enable. a 1 enables framer 2 interrupts. 2 frmr3ie framer 3 interrupt enable. a 1 enables framer 3 interrupts. 3 frmr4ie framer 4 interrupt enable. a 1 enables framer 4 interrupts. 4 frmr5ie framer 5 interrupt enable. a 1 enables framer 5 interrupts. 5 frmr6ie framer 6 interrupt enable. a 1 enables framer 6 interrupts. 6 frmr7ie framer 7 interrupt enable. a 1 enables framer 7 interrupts. 7 frmr8ie framer 8 interrupt enable. a 1 enables framer 8 interrupts. bit symbol description 0 fdl1_int facility data link 1 interrupt. a 1 indicates fdl1 generated an interrupt. 1 fdl2_int facility data link 2 interrupt. a 1 indicates fdl2 generated an interrupt. 2 fdl3_int facility data link 3 interrupt. a 1 indicates fdl3 generated an interrupt. 3 fdl4_int facility data link 4 interrupt. a 1 indicates fdl4 generated an interrupt. 4 fdl5_int facility data link 5 interrupt. a 1 indicates fdl5 generated an interrupt. 5 fdl6_int facility data link 6 interrupt. a 1 indicates fdl6 generated an interrupt. 6 fdl7_int facility data link 7 interrupt. a 1 indicates fdl7 generated an interrupt. 7 fdl8_int facility data link 8 interrupt. a 1 indicates fdl8 generated an interrupt. bit symbol description 0 fdl1ie facility data link 1 interrupt enable. a 1 enables fdl 1 interrupts. 1 fdl2ie facility data link 2 interrupt enable. a 1 enables fdl 2 interrupts. 2 fdl3ie facility data link 3 interrupt enable. a 1 enables fdl 3 interrupts. 3 fdl4ie facility data link 4 interrupt enable. a 1 enables fdl 4 interrupts. 4 fdl5ie facility data link 5 interrupt enable. a 1 enables fdl 5 interrupts. 5 fdl6ie facility data link 6 interrupt enable. a 1 enables fdl 6 interrupts. 6 fdl7ie facility data link 7 interrupt enable. a 1 enables fdl 7 interrupts. 7 fdl8ie facility data link 8 interrupt enable. a 1 enables fdl 8 interrupts. lucent technologies inc. 125 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. global register structure (continued) global control register (greg4) this register selects the source of the output second pulse (bit 0bit 2), interrupt 3-state control (bit 4), and inter- rupt polarity (bit 6). table 64. global control register (greg4) (004) device id and version registers (greg5 greg7) these bits define the device and version number of this framer circuit. table 65. device id and version registers (greg5 greg7) (005007) bit symbol description 0 secctrl2 second out p ut control. these bits determine which framer is used to source the output second pin: bit 0 bit 1 bit 2 0 0 0: framer 1 sources the second pin. 0 0 1: framer 2 sources the second pin. 0 1 0: framer 3 sources the second pin. 0 1 1: framer 4 sources the second pin. 1 0 0: framer 5 sources the second pin. 1 0 1: framer 6 sources the second pin. 1 1 0: framer 7 sources the second pin. 1 1 1: framer 8 sources the second pin. 1 secctrl1 2 secctrl0 3 reserved. 4itsc interrupt 3-state control. this bit alon g with bit 6 in this re g ister ( polarit y control ) allows the interrupt pin to be pro g rammed for active high, active low, wire-or, or wire- and operation, as described below: bit 4 bit 6 00pro g rams the interrupt pin to be active high ( 1-state ) when there is an inter- rupt condition and to be inactive low ( 0-state ) when the condition g oes awa y . 01pro g rams the interrupt pin to be active low ( 0-state ) when there is an inter- rupt condition and to be inactive high ( 1-state ) when the condition g oes awa y . 10 pro g rams the interrupt pin to be active high ( 1-state ) when there is an inter- rupt condition and to be inactive high-z ( 3-state ) when the condition g oes awa y . 11 pro g rams the interrupt pin to be active low ( 0-state ) when there is an inter- rupt condition and to be inactive high-z ( 3-state ) when the condition g oes awa y . 5 reserved. 6ipc interru p t polarit y control. a 1 inverts the polarity of the interrupt pin (negative polarity). 7 reserved. register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device code greg5 11 111000 device code greg6 00 000011 version # greg7 00 000010 preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 126 lucent technologies inc. lucent technologies inc. global register structure (continued) global control register (greg8) table 66. global control register (greg8) (008) bit symbol description 0lomux2 loss of clock out p ut control. these bits determine which framer is used to source the output lorlck and lopllck pin: bit 0 bit 1 bit 2 0 0 0: framer 1 sources the lorlck and lopllck pins. 0 0 1: framer 2 sources the lorlck and lopllck pins. 0 1 0: framer 3 sources the lorlck and lopllck pins. 0 1 1: framer 4 sources the lorlck and lopllck pins. 1 0 0: framer 5 sources the lorlck and lopllck pins. 1 0 1: framer 6 sources the lorlck and lopllck pins. 1 1 0: framer 7 sources the lorlck and lopllck pins. 1 1 1: framer 8 sources the lorlck and lopllck pins. 1lomux1 2lomux0 3 reserved. 4divmux2 divide clocks out p ut control. these bits determine which framer is used to source the output div-rlck, div-pllck, div-chick, chick-epll, and pllck-epll pins: bit 0 bit 1 bit 2 0 0 0: framer 1 sources the div-rlck, div-pllck, div-chick, chick-epll and pllck-epll pins. 0 0 1: framer 2 sources the div-rlck, div-pllck, div-chick, chick-epll and pllck-epll pins. 0 1 0: framer 3 sources the div-rlck, div-pllck, div-chick, chick-epll and pllck-epll pins. 0 1 1: framer 4 sources the div-rlck, div-pllck, div-chick, chick-epll and pllck-epll pins. 1 0 0: framer 5 sources the div-rlck, div-pllck, div-chick, chick-epll and pllck-epll pins. 1 0 1: framer 6 sources the div-rlck, div-pllck, div-chick, chick-epll and pllck-epll pins. 1 1 0: framer 7 sources the div-rlck, div-pllck, div-chick, chick-epll and pllck-epll pins. 1 1 1: framer 8 sources the div-rlck, div-pllck, div-chick, chick-epll and pllck-epll pins. 5divmux1 6divmux0 7 reserved. lucent technologies inc. 127 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. global register structure (continued) global pllck control register (greg9) this register selectively enables/disables an individual transmit framers internal clock synthesizer. setting all bits to 0 (the default condition) disables all transmit framer clock synthesizers, and allows an external source of pllck to drive the transmit framers. table 67. global pllck control register (greg9) (009) bit symbol description 0 eipllck1 enable transmit framer 1s internal pllck clock s y nthesizer. 1 eipllck2 enable transmit framer 2s internal pllck clock s y nthesizer. 2 eipllck3 enable transmit framer 3s internal pllck clock s y nthesizer. 3 eipllck4 enable transmit framer 4s internal pllck clock s y nthesizer. 4 eipllck5 enable transmit framer 5s internal pllck clock s y nthesizer. 5 eipllck6 enable transmit framer 6s internal pllck clock s y nthesizer. 6 eipllck7 enable transmit framer 7s internal pllck clock s y nthesizer. 7 eipllck8 enable transmit framer 8s internal pllck clock s y nthesizer. framer register architecture regbank1regbank8 contain the status and pro- grammable control registers for the framer and system chi interface channels frm1frm8. the base address for regbank1regbank8 is y00 (hex), where y = 29 for frm1frm8, respectively. within these register banks, the bit map is identical for frm1frm8. the framer registers are structures as shown in table 68. default values are given in the individual register definition tables. table 68. framer status and control blocks address range (hexadecimal) * the most significant digit, designated by y, is used to identify each framer (for framer 1framer 8, y = 29, respectively). the complete register map for the framer is given in table 182table 186. the address of the registers is shown in the table title with the most significant digit, designated by y, used to identify each framer (for framer 1framer 8, y = 29, respectively). all status registers are clocked with the internal framer receive line clock (rfrmck). bits in status registers frm_sr1 and frm_sr7 are set at the onset of the condition and are cleared on read when the given condition is no longer present. these registers can generate interrupts if the corre- sponding register bits are enabled in interrupt enable registers frm_pr0frm_pr7. on all 16-bit counter registers (frm_sr8 frm_sr51), both bytes are cleared only after reading both bytes. these status registers are two byte register pairs. these register pairs must be read in succession, with the lower byte read first followed by a read of higher byte. once a read is initiated on one of the bytes, the updating of that counter is disabled and remains disabled until both bytes are read. all events during this interval are lost. updating of the counter registers is stopped when all of the bits are set to 1. updating resumes after the registers are cleared on read. these register pairs may be read in any order, but they must be read in pairs, i.e., a read of 1 byte must be followed immediately by a read of the remain- ing byte of the pair. status registers frm_sr0frm_sr63 are clear-on- read (cor) registers. these registers are cleared by the framer internal received line clock (rfrmck). at least two rfrmck cycles (1.3 s for ds1 and 1.0 s for cept) must be allowed between successive reads of the same cor register to allow it to properly clear. framer register block status registers (cor) (y00y3f)* receive signaling registers (y40y5f)* parameter (configuration) registers (y60ya6)* transmit signaling registers (ye0yff)* preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 128 lucent technologies inc. lucent technologies inc. framer register architecture (continued) framer status/counter registers registers frm_sr0frm_sr63 report the status of each framer. all are clear-on-read, read-only registers. interrupt status register (frm_sr0) the interrupt pin (interrupt) goes active when a bit in this register and its associated interrupt enable bit in reg- isters frm_pr0frm_pr7 are set, and the interrupt for the framer block is enabled in register greg1. table 69. interrupt status register (frm_sr0) (y00) bit symbol description 0fac facility alarm condition. a 1 indicates a facility alarm occurred (go read frm_sr1). 1rac remote alarm condition. a 1 indicates a remote alarm occurred (go read frm_sr2). 2fae facility alarm event. a 1 indicates a facility alarm occurred (go read frm_sr3 and frm_sr4). 3ese errored second event. a 1 indicates an errored second event occurred (go read frm_sr5, frm_sr6, and frm_sr7). 4tssfe transmit signaling superframe event. a 1 indicates that a mos superframe block has been transmitted and the transmit signaling data buffers are ready for new data. 5rssfe receive signaling superframe event. a 1 indicates that a mos superframe block has been received and the receive signaling data buffers must be read. 6reserved. 7s96sr slc -96 stack ready. a 1 indicates that either the transmit framer slc -96 stack is ready for more data or the receive framer slc -96 stack contains new data. lucent technologies inc. 129 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. framer register architecture (continued) facility alarm condition register (frm_sr1) the bits in the facility alarm condition register (frm_sr1) indicate alarm state of the receive framer section. inter- rupts from this register are generated once at the onset of the alarm condition. if the alarm condition is still present at the time of the read, the bit will remain in the 1 state for the duration of the alarm condition. if the alarm condition is no longer present at the time of the read, then the bit is cleared on read. table 70. facility alarm condition register (frm_sr1) (y01) bit symbol description 0lfa loss of frame alignment. a 1 indicates the receive framer is in a loss of frame align- ment and is currently searching for a new alignment. 1lsfa loss of signaling superframe alignment. a 1 indicates the receive framer is in a loss of signaling superframe alignment in the ds1 framing formats. a search for a new sig- naling superframe alignment starts once frame alignment is established. lts16mfa loss of time slot 16 signaling multiframe alignment. a 1 indicates the receive framer is in a loss of time slot 16 signaling multiframe alignment in the cept mode. a search for a new time slot 16 signaling multiframe alignment starts once frame alignment is estab- lished. this bit is 0 when the TFRA08C13 is programmed for the transparent signaling mode, register frm_pr44 bit 0 (tsig) = 1. 2ltsfa loss of transmit superframe alignment. a 1 indicates superframe alignment pattern in the transmit facility data link as defined for slc -96 is lost. only valid for slc -96 mode. this bit is 0 in all other ds1 modes. lts0mfa loss of time slot 0 crc-4 multiframe alignment. a 1 indicates an absence of crc-4 multiframe alignment after initial basic frame alignment is established. a 0 indicates either crc-4 checking is disabled or crc-4 multiframe alignment has been success- fully detected. 3lfalr loss of frame alignment since last read. a 1 indicates that the lfa state indicated in bit 0 of this register is the same lfa state as the previous read. 4lbfa loss of biframe alignment. a 1 indicates that the cept biframe alignment pattern (alternating 10 in bit 2 of time slot 0 of each frame) in the receive system data is errored. this alignment pattern is required when transmitting the si or sa bits transparently. only valid in the cept mode. this bit is 0 in all other modes. 5rts16ais receive time slot 16 alarm indication signal. a 1 indicates the receive framer detected time slot 16 ais in the cept mode. this bit is 0 in the ds1 modes. 6auxp auxiliary pattern. a 1 indicates the detection of a valid auxp (unframed 1010 . . . pat- tern) in the cept mode. this bit is 0 in the ds1 modes. 7ais alarm indication signal. a 1 indicates the receive framer is currently receiving an ais pattern from its remote line end. preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 130 lucent technologies inc. lucent technologies inc. framer register architecture (continued) remote end alarm register (frm_sr2) a bit set to 1 indicates the receive framer has recently received the given alarm. interrupts from this register are generated once at the beginning of the alarm condition. if the alarm is still present at the time of the read, the bit will remain in the 1 state for the duration of the alarm condition. if the alarm condition is no longer present at the time of the read, then the bit is cleared on read. table 71. remote end alarm register (frm_sr2) (y02) bit symbol description 0rfa remote framer alarm. a 1 indicates the receive framer detected a remote frame (yel- low) alarm. 1rjya remote japanese yellow alarm. a 1 indicates the receive framer detected the japa- nese format remote frame alarm. rts16mfa remote multiframe alarm. a 1 indicates the receive framer detected a time slot 16 remote frame alarm in the cept mode. 2crebit continuous received e bits. a 1 indicates the detection of a five-second interval con- taining 3 991 e bit = 0 events in each second. this bit is 0 in the ds1 mode. 3sa6 = 8 received sa6 = 8. a 1 indicates the receive framer detected an sa6 code equal to 1000. this bit is 0 in the ds1 mode. 4sa6 = a received sa6 = a. a 1 indicates the receive framer detected an sa6 code equal to 1010. this bit is 0 in the ds1 mode. 5sa6 = c received sa6 = c. a 1 indicates the receive framer detected an sa6 code equal to 1100. this bit is 0 in the ds1 mode. 6sa6 = e received sa6 = e. a 1 indicates the receive framer detected an sa6 code equal to 1110. this bit is 0 in the ds1 mode. 7 sa6 = f received sa6 = f. a 1 indicates the receive framer detected an sa6 code equal to 1111. this bit is 0 in the ds1 mode. lucent technologies inc. 131 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. framer register architecture (continued) facility errored event register (frm_sr3) a bit set to 1 indicates the receive framer has recently received the given errored event. table 72. facility errored event register-1 (frm_sr3) (y03) bit symbol description 0lfv line format violation. a 1 indicates the receive framer detected a bipolar line coding or excessive zeros violation. 1fbe frame-bit errored. a 1 indicates the receive framer detected a frame-bit or frame align- ment pattern error. 2 crce crc errored. a 1 indicates the receive framer detected crc errors. 3ece excessive crc errors. a 1 indicates the receive framer detected an excessive crc errored condition. this bit is only valid in the esf and cept with crc-4 modes; other- wise, it is 0. 4rebit received e bit = 0. a 1 indicates the receive framer detected an e bit = 0 in either frame 13 or 15 of the time slot 0 of crc-4 multiframe. this bit is 0 in the ds1 modes. 5 lcrcatmx lack of crc-4 multiframe alignment timer expire indication. a 1 indicates that either the 100 ms or the 400 ms crc-4 interworking timer expired. active only immedi- ately after establishment of the initial basic frame alignment. this bit is 0 in the ds1 modes. 6slipo receive elastic store slip: buffer overflow. a 1 indicates the receive elastic store per- formed a control slip due to an elastic buffer overflow condition. 7slipu receive elastic store slip: buffer underflow. a 1 indicates the receive elastic store performed a control slip due to an elastic buffer underflow condition. preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 132 lucent technologies inc. lucent technologies inc. framer register architecture (continued) table 73. facility event register-2 (frm_sr4) (y04) bit symbol description 0nfa new frame alignment. a 1 indicates the receive framer established a new frame align- ment which differs from the previous alignment. 1ssfa signaling superframe alignment. a 1 indicates the receive framer has established the signaling superframe alignment. in the sf modes (d4 and slc -96) and cept modes, this alignment is established only after primary frame alignment is determined. 2llboff t1 line loopback off code detect. a 1 indicates the receive framer detected the ds1 line loopback disable code in the payload. this code is defined in at&t technical refer- ence 62411 as a framed 001 pattern where the frame bit is inserted into the pattern. bfa new biframe alignment established. a 1 indicates the transmit framer has established a biframe alignment for the transmission of transparent si and or sa bits from the system data in the cept mode. 3 llbon t1 line loopback on code detect. a 1 indicates the receive framer detected the line loopback enable code in the payload. this code is defined in at&t technical reference 62411 as a framed 00001 pattern where the frame bit is inserted into the pattern. cma new cept crc-4 multiframe alignment. a 1 indicates the cept crc-4 multiframe alignment in the receive framer has been established. 4fdl-plbon esf fdl payload loopback on code detect. a 1 indicates the receive framer detected the line loopback enable code in the payload. this code is defined in ansi t1.403-1995 as a 1111111100101000 pattern in the facility data link, where the leftmost bit is the msb. slc rfsr slc -96 receive fdl stack ready. a 1 indicates that the receive fdl stack should be read. this bit is cleared on read. data in the receive fifo must be read within 9 ms of this interrupt. this bit is not updated during loss of frame or signaling superframe align- ment. 5fdl-plboff esf fdl payload loopback off code detect. a 1 indicates the receive framer detected the line loopback disable code in the payload. this code is defined in ansi t1.403-1995 as a 1111111101001100 pattern in the facility data link, where the leftmost bit is the msb. slc tfsr slc -96 transmit fdl stack ready. a 1 indicates that the transmit fdl stack is ready for new data. this bit is cleared on read. data written within 9 ms of this interrupt will be transmitted in the next slc -96 d-bit superframe interval. 6fdl-llbon esf fdl line loopback on code detect. a 1 indicates the receive framer detected the line loopback enable code in the payload. this code is defined in ansi t1.403-1995 as a 1111111101110000 pattern in the facility data link, where the leftmost bit is the msb. rsasr cept receive sa stack ready. a 1 indicates that the receive sa6 stack should be read. this bit is clear on the first access to the sa receive stack or at the beginning of frame 0 of the crc-4 double-multiframe. data in the receive fifo must be read within 4 ms of this interrupt. this bit is not updated during lfa. 7fdl-llboff esf fdl line loopback off code detect. a 1 indicates the receive framer detected the line loopback disable code in the payload. this code is defined in ansi t1.403-1995 as a 1111111100011100 pattern in the facility data link, where the leftmost bit is the msb. tsasr cept transmit sa stack ready. a 1 indicates that the transmit sa stack is ready for new data. this bit is cleared on the first access to the sa transmit stack or at the begin- ning of frame 0 of the crc-4 double multiframe. data written within 4 ms of this interrupt will be transmitted in the next crc-4 double multiframe interval. lucent technologies inc. 133 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. framer register architecture (continued) the following registers are dedicated to the exchange termination and its remote end interface. the alarm condi- tions to trigger errored seconds and severely errored seconds are defined in table 32 and the et and et-re enable registers, frm_pr14 and frm_pr15. the thresholds are defined in registers frm_pr11frm_pr13. table 74. exchange termination and exchange termination remote end interface status register (frm_sr5) (y05) bit symbol description 0etes et errored second. a 1 indicates the receive framer detected an errored second at the exchange termination (et). 1etbes et bursty errored second. a 1 indicates the receive framer detected a bursty errored second at the et. 2etses et severely errored second. a 1 indicates the receive framer detected a severely errored second at the et. 3etuas et unavailable state. a 1 indicates the receive framer has detected at least ten con- secutive severely errored seconds. upon detecting ten consecutive nonseverely errored seconds, the receive framer will clear this bit. itu recommendation g.826 is used resulting in a ten-second delay in the reporting of this condition. 4 etrees et-re errored second. a 1 indicates the receive framer detected an errored second at the exchange termination remote end (et-re). 5 etrebes et-re bursty errored second. a 1 indicates the receive framer detected a bursty errored second at the et-re. 6 etreses et-re severely errored second. a 1 indicates the receive framer detected a severely errored second at the et-re. 7 etreuas et-re unavailable state. a 1 indicates the receive framer has detected at least ten consecutive severely errored seconds. upon detecting ten consecutive nonseverely errored seconds, the receive framer will clear this bit. itu recommendation g.826 is used resulting in a ten-second delay in the reporting of this condition. preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 134 lucent technologies inc. lucent technologies inc. framer register architecture (continued) the following status registers are dedicated to the nt1 and the nt1 remote end (nt1-re) interface. the alarm conditions to evaluate errored seconds and severely errored seconds are defined in table 32 and the nt1 and nt1-re enable registers, frm_pr16frm_pr18. the thresholds are defined in registers frm_pr11 frm_pr13. table 75. network termination and network termination remote end interface status register (frm_sr6) (y06) bit symbol description 0ntes nt errored second. a 1 indicates the receive framer detected an errored second at the network termination (nt). 1ntbes nt bursty errored second. a 1 indicates the receive framer detected a bursty errored second at the nt. 2ntses nt severely errored second. a 1 indicates the receive framer detected a severely errored second at the nt. 3ntuas nt unavailable state. a 1 indicates the receive framer has detected at least ten consec- utive severely errored seconds. upon detecting ten consecutive nonseverely errored sec- onds, the receive framer will clear this bit. itu recommendation g.826 is used resulting in a ten-second delay in the reporting of this condition. 4ntrees nt-re errored second. a 1 indicates the receive framer detected an errored second at the exchange termination remote end (et-re). 5 ntrebes nt-re bursty errored second. a 1 indicates the receive framer detected a bursty errored second at the et-re. 6 ntreses nt-re severely errored second. a 1 indicates the receive framer detected a severely errored second at the nt-re. 7 ntreuas nt-re unavailable state. a 1 indicates the receive framer has detected at least ten consecutive severely errored seconds. upon detecting ten consecutive nonseverely errored seconds, the receive framer will clear this bit. itu recommendation g.826 is used resulting in a ten-second delay in the reporting of this condition. lucent technologies inc. 135 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. framer register architecture (continued) bit 0bit 4 in this register are set high when the receive framer comes out of the unavailable state, while bit 4bit 7 report detection of the receive test patterns. bits 4 and 5 are cleared only after register frm_pr70 bit 2 is set to 0. table 76. facility event register (frm_sr7) (y07) * it is possible for one of these bits to be set to 1, if the received line data is all zeros. bipolar violation counter register (frm_sr8frm_sr9) this register contains the 16-bit count of received bipolar violations, line code violations, or excessive zeros. table 77. bipolar violation counter registers (frm_sr8frm_sr9) (y08y09) frame bit errored counter register (frm_sr10frm_sr11) this register contains the 16-bit count of framing bit errors. framing bit errors are not counted during loss of frame alignment. table 78. framing bit error counter registers (frm_sr10frm_sr11) (y0ay0b) bit symbol description 0ouas out of unavailable state. a 1 indicates the receive framer detected ten consecutive seconds that were not severely errored while in the unavailable state at the et. 1erouas out of unavailable state at the et-re. a 1 indicates the receive framer detected ten consecutive seconds that were not severely errored while in the unavailable state at the et-re. 2nt1ouas out of unavailable state at the nt1. a 1 indicates the receive framer detected ten con- secutive seconds that were not severely errored while in the unavailable state at the nt. 3nrouas out of unavailable state nt1-re. a 1 indicates the receive framer detected ten con- secutive seconds that were not severely errored while in the unavailable state at the nt- re. 4 detect test pattern detected. a 1 indicates the pattern detector has locked onto the pattern specified by the ptrn configuration bits defined in register frm_pr70. 5 ptrnber test pattern bit error. a 1 indicates the pattern detector has found one or more single bit errors in the pattern that it is currently locked onto. 6rpsuedo receiving pseudorandom pattern. a 1 indicates the receive framer pattern monitor circuit is currently detecting the 2 15 C 1 pseudorandom pattern*. 7 rquasi receiving quasi-random pattern. a 1 indicates the receive framer pattern monitor cir- cuit is currently detecting the 2 20 C 1 quasi-random pattern*. register byte bit symbol description frm_sr8 msb 70 bpv15bpv8 bpvs counter. frm_sr9 lsb 70 bpv7bpv0 bpvs counter. register byte bit symbol description frm_sr10 msb 70 fbe15fbe8 frame bit rrored counter. frm_sr11 lsb 70 fbe7fbe0 frame bit errored counter. preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 136 lucent technologies inc. lucent technologies inc. framer register architecture (continued) crc error counter register (frm_sr12frm_sr13) this register contains the 16-bit count of crc errors. crc errors are not counted during loss of crc multiframe alignment. table 79. crc error counter registers (frm_sr12frm_sr13) (y0cy0d) e-bit counter register (frm_sr14frm_sr15) this register contains the 16-bit count of received e bit = 0 events. e bits are not counted during loss of cept crc-4 multiframe alignment. table 80. e-bit counter registers (frm_sr14frm_sr15) (y0ey0f) crc-4 errors at nt1 from nt2 counter registers (frm_sr16frm_sr17) this register contains the 16-bit count of each occurrence of sa6 code 001x, detected synchronously to the cept crc-4 multiframe. table 81. crc-4 errors at nt1 from nt2 counter registers (frm_sr16frm_sr17) (y10y11) e bit at nt1 from nt2 counter registers (frm_sr18frm_sr19) this register contains the 16-bit count of each occurrence of sa6 code 00x1, detected synchronously to the cept crc-4 multiframe. e bits are not counted during loss of cept crc-4 multiframe alignment. table 82. e bit at nt1 from nt2 counter (frm_sr18frm_sr19) (y12y13) register byte bit symbol description frm_sr12 msb 70 cec15cec8 crc errored counter. frm_sr13 lsb 70 cec7cec0 crc errored counter. register byte bit symbol description frm_sr14 msb 70 rec15rec8 e-bit counter. frm_sr15 lsb 70 rec7rec0 e-bit counter. register byte bit symbol description frm_sr16 msb 70 cnt15cnt8 crc-4 errors at nt1 counter. frm_sr17 lsb 70 cnt7cnt0 crc-4 errors at nt1 counter. register byte bit symbol description frm_sr18 msb 70 ent15ent8 e bit at nt1 counter. frm_sr19 lsb 70 ent7ent0 e bit at nt1 counter. lucent technologies inc. 137 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. framer register architecture (continued) the following status registers, frm_sr20frm_sr51, contain the 16-bit count of errored seconds, bursty errored seconds, severely errored seconds, and unavailable seconds at the et, et-re, nt1, and nt1-re termi- nals. ds1 error conditions are reported in the et errored registers frm_sr20frm_sr35. table 83. et errored seconds counter (frm_sr20frm_sr21) (y14y15) table 84. et bursty errored seconds counter (frm_sr22frm_sr23) (y16y17) table 85. et severely errored seconds counter (frm_sr24frm_sr25) (y18y19) table 86. et unavailable seconds counter (frm_sr26frm_sr27) (y1ay1b) table 87. et-re errored seconds counter (frm_sr28frm_sr29) (y1cy1d) table 88. et-re bursty errored seconds counter (frm_sr30frm_sr31) (y1ey1f) table 89. et-re severely errored seconds counter (frm_sr32frm_sr33) (y20y21) register byte bit symbol description frm_sr20 msb 70 etes15etes8 et errored seconds counter. frm_sr21 lsb 70 etes7etes0 et errored seconds counter. register byte bit symbol description frm_sr22 msb 70 etbes15etbes8 et bursty errored seconds counter. frm_sr23 lsb 70 etbes7etbes0 et bursty errored seconds counter. register byte bit symbol description frm_sr24 msb 70 etses15etses8 et severely errored seconds counter. frm_sr25 lsb 70 etses7etses0 et severely errored seconds counter. register byte bit symbol description frm_sr26 msb 70 etus15etus8 et unavailable seconds counter bits. frm_sr27 lsb 70 etus7etus0 et unavailable seconds counter bits. register byte bit symbol description frm_sr28 msb 70 etrees15etrees8 et-re errored seconds counter. frm_sr29 lsb 70 etrees7etrees0 et-re errored seconds counter. register byte bit symbol description frm_sr30 msb 70 etrebes15etrebes8 et-re bursty errored seconds counter. frm_sr31 lsb 70 etrebes7etrebes0 et-re bursty errored seconds counter. register byte bit symbol description frm_sr32 msb 70 etreses15etreses8 et-re severely errored seconds counter. frm_sr33 lsb 70 etreses7etreses0 et-re severely errored seconds counter. preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 138 lucent technologies inc. lucent technologies inc. framer register architecture (continued) table 90. et-re unavailable seconds counter (frm_sr34frm_sr35) (y22y23) table 91. nt1 errored seconds counter (frm_sr36frm_sr37) (y24y25) table 92. nt1 bursty errored seconds counter (frm_sr38frm_sr39) (y26y27) table 93. nt1 severely errored seconds counter (frm_sr40frm_sr41) (y28y29) table 94. nt1 unavailable seconds counter (frm_sr42frm_sr43) (y2ay2b) table 95. nt1-re errored seconds counter (frm_sr44frm_sr45) (y2cy2d) table 96. nt1-re bursty errored seconds counter (frm_sr46frm_sr47) (y2ey2f) table 97. nt1-re severely errored seconds counter (frm_sr48frm_sr49) (y30y31) register byte bit symbol description frm_sr34 msb 70 etreus15etreses8 et-re unavailable seconds counter. frm_sr35 lsb 70 etreses7etreses0 et-re unavailable seconds counter. register byte bit symbol description frm_sr36 msb 70 ntes15ntes8 nt1 errored seconds counter. frm_sr37 lsb 70 ntes7ntes0 nt1 errored seconds counter. register byte bit symbol description frm_sr38 msb 70 ntbes15ntbes8 nt1 bursty errored seconds counter. frm_sr39 lsb 70 ntbes7ntbes0 nt1 bursty errored seconds counter. register byte bit symbol description frm_sr40 msb 70 ntses15ntses8 nt1 severely errored seconds counter. frm_sr41 lsb 70 ntses7ntses0 nt1 severely errored seconds counter. register byte bit symbol description frm_sr42 msb 70 ntus15ntus8 nt1 unavailable seconds counter bits. frm_sr43 lsb 70 ntus7ntus0 nt1 unavailable seconds counter bits. register byte bit symbol description frm_sr44 msb 70 ntrees15ntrees8 nt1-re errored seconds counter. frm_sr45 lsb 70 ntrees7ntrees0 nt1-re errored seconds counter. register byte bit symbol description frm_sr46 msb 70 ntrebes15ntrebes8 nt1-re bursty errored seconds counter. frm_sr47 lsb 70 ntrebes7ntrebes0 nt1-re bursty errored seconds counter. register byte bit symbol description frm_sr48 msb 70 ntreses15ntreses8 nt1-re severely errored seconds counter. frm_sr49 lsb 70 ntreses7ntreses0 nt1-re severely errored seconds counter. lucent technologies inc. 139 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. framer register architecture (continued) table 98. nt1-re unavailable seconds counter (frm_sr50frm_sr51) (y32y33) received not-fas ts0 rsa register (frm_sr52) this register contains the last (since last read) valid received rsa8 rsa4 bits, a bit, and si bit of not-fas time slot 0 and the si bit of fas time slot 0 while the receive framer was in basic frame alignment. table 99. receive not-fas ts0 register (frm_sr52) (y34) received sa register (frm_sr53) this register contains the last (since last read) valid time slot 16 spare bits of the frame containing the time slot 16 signaling multiframe alignment. these bits are updated only when the receive framer is in signaling multiframe alignment. table 100. receive sa register (frm_sr53) (y35) slc- 96 fdl/cept sa receive stack (frm_sr54frm_sr63) in the slc -96 frame format, frm_sr54 through frm_sr58 contain the received slc -96 facility data link data block. when the framer is in a loss of frame alignment or loss of signaling superframe alignment, these registers are not updated. note: the rsp[1:4] are the received spoiler bits. table 10 1 . slc- 96 fdl receive stack (frm_sr54frm_sr63) (y36y3f) register byte bit symbol description frm_sr50 msb 70 ntreus15ntreus8 nt1-re unavailable seconds counter bits. frm_sr51 lsb 70 ntreus7ntreus0 nt1-re unavailable seconds counter bits. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 not-fas bit 1 ( cept without crc-4 ) or frame 15 e bit ( cept with crc-4 ) fas bit 1 ( cept without crc-4 ) or frame 13 e bit ( cept with crc-4 ) a bit sa4 sa5 sa6 sa7 sa8 bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 00000x2x1x0 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 frm_sr54 0 0 r-0 r-0 r-0 r-1 r-1 r-1 frm_sr55 0 0 r-0 r-0 r-0 r-1 r-1 r-1 frm_sr56 rc1 rc2 rc3 rc4 rc5 rc6 rc7 rc8 frm_sr57 rc9 rc10 rc11 rspb1 = 0 rspb2 = 1 rspb3 = 0 rm1 rm2 frm_sr58 rm3 ra1 ra2 rs1 rs2 rs3 rs4 rspb4 = 1 frm_sr59 frm_sr61 0000 0 000 preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 140 lucent technologies inc. lucent technologies inc. framer register architecture (continued) in the cept frame format, frm_sr54 through frm_sr63 contain the received sa4 through sa8 from the last valid crc-4 double-multiframe. in non-crc-4 mode, these registers are only updated during a basic frame aligned state. in crc-4 mode, these registers are only updated during the crc-4 multiframe alignment state. table 102. cept sa receive stack (frm_sr54frm_sr63) (y36y3f) the receive framer stores the current second of the ansi performance report message transmitted to the remote end in registers frm_sr62 and frm_sr63. the structure of the prm status registers is shown in table 103. table 103. transmit framer ansi performance report message status register structure received signaling registers: ds1 format table 104. received signaling registers: ds1 format (frm_rsr0frm_rsr23) (y40y58) * bit 6 and bit 5 of the ds1 receive signaling registers are copied from bit 6 and bit 5 of the ds1 transmit signaling register s. register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 frm_sr54 sa4-1 sa4-3 sa4-5 sa4-7 sa4-9 sa4-11 sa4-13 sa4-15 frm_sr55 sa4-17 sa4-19 sa4-21 sa4-23 sa4-25 sa4-27 sa4-29 sa4-31 frm_sr56 sa5-1 sa5-3 sa5-5 sa5-7 sa5-9 sa5-11 sa5-13 sa5-15 frm_sr57 sa5-17 sa5-19 sa5-21 sa5-23 sa5-25 sa5-27 sa5-29 sa5-31 frm_sr58 sa6-1 sa6-3 sa6-5 sa6-7 sa6-9 sa6-11 sa6-13 sa6-15 frm_sr59 sa6-17 sa6-19 sa6-21 sa6-23 sa6-25 sa6-27 sa6-29 sa6-31 frm_sr60 sa7-1 sa7-3 sa7-5 sa7-7 sa7-9 sa7-11 sa7-13 sa7-15 frm_sr61 sa7-17 sa7-19 sa7-21 sa7-23 sa7-25 sa7-27 sa7-29 sa7-31 frm_sr62 sa8-1 sa8-3 sa8-5 sa8-7 sa8-9 sa8-11 sa8-13 sa8-15 frm_sr63 sa8-17 sa8-19 sa8-21 sa8-23 sa8-25 sa8-27 sa8-29 sa8-31 transmit framer prm status bytes tsprm b7 tsprm b6 tsprm b5 tsprm b4 tsprm b3 tsprm b2 tsprm b1 tsprm b0 frm_sr62 g3 lv g4 u1 u2 g5 sl g6 frm_sr63 fe se lb g1 r g2 nm nl received signal registers bit 7 bit 6 * bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ds1 received si g nalin g re g isters ( 023 ) pgf x dcba voice channel with 16-state si g nalin g x 00 x dcba voice channel with 4-state si g nalin g x 01 xxx ba voice channel with 2-state si g nalin g x 11 xxxx a data channel x 10 xxxxx lucent technologies inc. 141 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. framer register architecture (continued) receive signaling registers: cept format table 105. receive signaling registers: cept format (frm_rsr0frm_rsr31) (y40y5f) * in psco or psc1 signaling mode, this bit is undefined. framer parameter/control registers registers frm_pr0frm_pr70 define the mode configuration of each framer. all are read/write registers. these registers are initially set to a default value upon a hardware reset, which is indicated in the register definition. interrupt group enable registers (frm_pr0frm_pr7) the bits in this register group enable the status registers frm_sr0frm_sr7 to assert the interrupt pin. the default value of these registers is 00 (hex). frm_pr0 is the primary interrupt group enable register which enables the event groups in interrupt status register frm_sr0. a bit set to 1 in this register enables the corresponding bit in the interrupt status register frm_sr0 to assert the interrupt pin. frm_pr1frm_pr7 are the secondary interrupt enable registers. a bit set to 1 in these registers enables the corresponding bit in the status register to assert the interrupt pin. table 106. summary of interrupt group enable registers (frm_pr0frm_pr7) (y60y67) receive signal registers bit 7 bit 65 bit 4 * bit 3 bit 2 bit 1 bit 0 frm_rsr1frm_rsr15 pxe [ 1:15 ] d [ 1:15 ] c [ 1:15 ] b [ 1:15 ] a [ 1:15 ] frm_rsr[17:31] pxe [ 17:31 ] d [ 17:31 ] c [ 17:31 ] b [ 17:31 ] a [ 17:31 ] parameter/ control re g ister status register enabled status register bit 7 status re g ister bit 6 status register bit 5 status register bit 4 status register bit 3 status register bit 2 status register bit 1 status register bit 0 frm_pr0 frm_sr0 s96sr reserved rssfe tssfe ese ( read frm_sr5, frm_sr6, and frm_sr7 ) fae ( read frm_sr3 and frm_sr4 ) rac ( read frm_sr2 ) fac ( read frm_sr1 ) frm_pr1 frm_sr1 ais auxp rts16ais lbfa lfalr ltsfa ( lts0mfa ) lsfa ( lts16mfa ) lfa frm_pr2 frm_sr2 rsa6=f rsa6=e rsa6=c rsa6=a rsa6=8 crebit rjya ( rts16mfa ) rfa frm_pr3 frm_sr3 slipu slipo lcrcatmx rebit ece crce fbe lfv frm_pr4 frm_sr4 fdl_llboff ( tsasr ) fdl_llbon ( rsasr ) fdl_plboff ( slc tfsr ) fdl_plbon ( slc rfsr ) llbon ( cma ) llboff ( bfa ) ssfa cfa frm_pr5 frm_sr5 etreuas etreses etrebes etrees etuas etses etbes etes frm_pr6 frm_sr6 ntreuas ntreses ntrebes ntrees ntuas ntses ntbes ntes frm_pr7 frm_sr7 rquasi rpsuedo ptrnber detect nrouas nt1ouas erouas ouas preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 142 lucent technologies inc. lucent technologies inc. framer register architecture (continued) primary interrupt enable register (frm_pr0) the default value of this register is 00 (hex). table 107. primary interrupt group enable register (frm_pr0) (y60) secondary interrupt enable registers (frm_pr1frm_pr7) a bit set to 1 in registers frm_pr1frm_pr7 enables the generation of interrupts whenever the corresponding bit in registers frm_sr1frm_sr7 is set. the default value of these registers is 00 (hex). table 108. interrupt enable register (frm_pr1) (y61) table 109. interrupt enable register (frm_pr2) (y62) table 110. interrupt enable register (frm_pr3) (y63) bit symbol description 0sr1ie status register 1 interrupt enable bit. a 1 enables register frm_sr1 event inter- rupts. 1sr2ie status register 2 interrupt enable bit. a 1 enables register frm_sr2 event inter- rupts. 2sr34ie status registers 3 and 4 interrupt enable bit. a 1 enables registers frm_sr3 and frm_sr4 event interrupts. 3sr567ie status registers 5, 6, and 7 interrupt enable bit. a 1 enables registers frm_sr5, frm_sr6, and frm_sr7 event interrupts. 4tsrie transmit signaling ready interrupt enable bit. a 1 enables interrupts when transmit signaling buffers are ready (mos mode). 5rsrie receive signaling ready interrupt enable bit. a 1 enables interrupts when receive signaling buffers are ready (mos mode). 6 reserved . write to 0. 7slcie slc -96 interrupt enable bit. a 1 enables interrupts when slc -96 receive or transmit stacks are ready. bit symbol description 07 sr1b0ie sr1b7ie status register 1 interrupt enable. a 1 enables events monitored in register frm_sr1 to generate interrupts. each bit position in this enable register corresponds to the same bit position in the status register. bit s y mbol description 07 sr2b0ie sr2b7ie status register 2 interrupt enable. a 1 enables events monitored in register frm_sr2 to generate interrupts. each bit position in this enable register corresponds to the same bit position in the status register. bit symbol description 07 sr3b0ie sr3b7ie status register 3 interrupt enable. a 1 enables events monitored in register frm_sr3 to generate interrupts. each bit position in this enable register corresponds to the same bit position in the status register. lucent technologies inc. 143 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. framer register architecture (continued) table 111. interrupt enable register (frm_pr4) (y64) table 112. interrupt enable register (frm_pr5) (y65) table 113. interrupt enable register (frm_pr6) (y66) table 114. interrupt enable register (frm_pr7) (y67) framer mode option register (frm_pr8) the default value of this register is c0 (hex). table 115. framer mode bits decoding (frm_pr8) (y68) bit symbol description 07 sr4b0ie sr4b7ie status register 4 interrupt enable. a 1 enables events monitored in register frm_sr4 to generate interrupts. each bit position in this enable register corresponds to the same bit position in the status register. bit symbol description 07 sr5b0ie sr5b7ie status register 5 interrupt enable. a 1 enables events monitored in register frm_sr5 to generate interrupts. each bit position in this enable register corresponds to the same bit position in the status register. bit symbol description 07 sr6b0ie sr6b7ie status register 6 interrupt enable. a 1 enables events monitored in register frm_sr6 to generate interrupts. each bit position in this enable register corresponds to the same bit position in the status register. bit symbol description 07 sr7b0ie sr7b7ie status register 7 interrupt enable. a 1 enables events monitored in register frm_sr7 to generate interrupts. each bit position in this enable register corresponds to the same bit position in the status register. frm_pr8 frame format bit 7 bit 6 bit 5 bit 4 fmode 4 bit 3 fmode 3 bit 2 fmode 2 bit 1 fmode 1 bit 0 fmode 0 esf xxx00000 d4 xxx00001 dds xxx00010 dds with fdl xxx00011 slc -96 xxx00100 transmit esf receive d4 xxx10000 transmit d4 receive esf xxx10001 cept with no crc-4 pcs mode 0 x x x 01001 pcs mode 1xxx01010 cept with crc-4 pcs mode 1 x x x 01101 pcs mode 0xxx01110 preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 144 lucent technologies inc. lucent technologies inc. framer register architecture (continued) table 116. line code option bits decoding (frm_pr8) (y68) framer crc control option register (frm_pr9) this register defines the crc options for the framer. the default setting is 00 (hex). table 117. crc option bits decoding (frm_pr9) (y69) line code format bit 7 lc2 bit 6 lc1 bit 5 lc0 bit 4 bit 3 bit 2 bit 1 bit 0 b8zs ( t/r ) 0 0 0 xxxxx zcs ( t/r ) 0 0 1 xxxxx hdb3 ( t/r ) 0 1 0 xxxxx sin g le rail ( default ) 1 1 0 xxxxx ami ( t/r ) 0 1 1 xxxxx b8zs ( t ) , ami ( r ) 1 0 0 xxxxx zcs ( t ) , b8zs ( r ) 1 0 1 xxxxx ami ( t ) , b8zs ( r ) 1 1 1 xxxxx frm_pr9 crc options bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 loss of frame ali g nment due to excessive crc errors ( esf 3 320, cept 3 915 in a one-second interval ) 0xxxxx1 1 crc-4 with 100 ms timer 0xxxx1x1 crc-4 interworkin g search with 400 ms timer 0 x x x 1 x x 1 crc-4 with 990 reb counter 0 x x 1 x x x 1 crc-4 with 990 reb counter: a bit = 1 restart 0 x 1 1 x x x 1 crc-4 with 990 reb counter: sa6-f or sa6-e restart 0 1 x 1 x x x 1 xcrc-4/r-no crc-4 1 xxxxxx0 x-nocrc-4/rcrc4 1 xxxxxx1 crc default mode ( no crc ) 00000000 lucent technologies inc. 145 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. framer register architecture (continued) alarm filter register (frm_pr10) the bits in this register enable various control options. the default setting is 00 (hex). table 118. alarm filter register (frm_pr10) (y6a) bit 6 and bit 7 of frm_pr10 control the evaluation of the bursty errored parameter as defined in table 119 below. the est parameter refers to the errored second threshold defined in register frm_pr11. the sest parameter refers to the severely errored second threshold defined in registers frm_pr12 and frm_pr13 table 119. errored event threshold definition bit symbol description 0ssa6m s y nchronous sa6 monitorin g . a 0 enables the as y nchronous monitorin g of the sa6 codes relative to the receive crc-4 submultiframe. a 1 enables s y nchronous monitorin g of the sa6 pattern relative to the receive crc-4 submultiframe. 1aism ais detection mode. a 0 enables the detection of received line ais as described in etsi draft prets 300 233:1992. a 1 enables the detection of received line ais as described in itu rec. g.775. 2feren fer enable ( ds1 onl y) . a 0 enables onl y the detection of f t framin g bit errors in d4 and slc -96 modes. a 1 enables the detection of f t and f s framin g bit errors. nffe not fas framin g bit error control ( cept onl y) . a 0 enables the monitorin g of errored fas and errored not fas frames in the framin g bit error counter, re g isters frm_sr10 and frm_sr11. a 1 enables the monitorin g of onl y errored fas frames in this error counter. 3 cnuclben cnuclb enable ( cept onl y) . a 0 enables pa y load loopback with re g enerated framin g and crc bits in re g ister frm_pr24. a 1 enables cept nailed-up connect loopback in re g ister frm_pr24. 4 reserved. set to 0. 5rabf receive a-bit filter ( cept onl y) . a 0 makes the occurrence of three consecutive a bit = 1 events assert and three consecutive a bit = 0 events deassert the remote frame alarm, re g ister frm_sr2 bit 0. a 1 enables the occurrence of a sin g le a-bit event to deassert the remote frame alarm. bit 7, frm_pr10 esm1 bit 6, frm_pr10 esm0 errored second (es) definition bursty errored second (bes) definition severely errored second (ses) definition 0 0 default values in table 32. 0 1 es = 1 when: errored events > est bes = 0 ses = 1 when: errored events > sest other combinations reserved. preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 146 lucent technologies inc. lucent technologies inc. framer register architecture (continued) errored second threshold register (frm_pr11) this register defines the errored event threshold for an errored second (es). a one-second interval with errors less than the es threshold value will not be detected as an errored second. programming 00 (hex) into this register dis- ables the errored second threshold monitor circuitry if register frm_pr10 bit 6 = 1 and bit 7 = 0. the default value of this register is 00 (hex). table 120. errored second threshold register (frm_pr11) (y6b) severely errored second threshold register (frm_pr12frm_pr13) this 16-bit register defines the errored event threshold for a severely errored second (ses). a one-second interval with errors less than the ses threshold value is not a severely errored second. programming 00 (hex) into these two registers disables the severely errored second threshold monitor circuitry if register frm_pr10 bit 6 = 1 and bit 7 = 0. the default value of these registers is 00 (hex). table 121. severely errored second threshold registers (frm_pr12frm_pr13) (y6cy6d) et1 errored event enable register (frm_pr14) these bits enable the errored events used to determine errored and severely errored seconds at the local et inter- face. etslip, etais, etlmfa, and etlfa are the slip, ais, lmfa, and lfa errored events, respectively, as referred to the local et interface. a 1 in the bit position enables the corresponding errored event. the default value of this register is 00 (hex). table 122. et1 errored event enable register (frm_pr14) (y6e) et1 remote end errored event enable register * (frm_pr15) these bits enable the errored events used to determine errored and severely errored seconds at the et's remote end interface. etresa6-f , etresa6-e , etresa6-8 , etrerfa , etreslip , etreais , etrelmfa , and etrelfa are the sa6-f , sa6-e , sa6-8 , rfa , slip , ais , lmfa , and lfa errored events, respectively, as referred to the et remote end interface. a 1 in the bit position enables the corresponding errored event. the default value of this reg- ister is 00 (hex). table 123. et1 remote end errored event enable register (frm_pr15) (y6f) * one occurrence of any one of these events causes an errored second count increment and a severely errored second count increm ent. register symbol description frm_pr11 est7est0 es threshold register. register symbol description frm_pr12 sest15sest8 ses msb threshold register. frm_pr13 sest7sest0 ses lsb threshold register. register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 frm_pr14 0 0 0 0 etslip etais etlmfa etlfa register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 frm_pr15 etresa6-f etresa6-e etresa6-8 etrerfa etreslip etreais etrelmfa etrelfa lucent technologies inc. 147 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. framer register architecture (continued) nt1 errored event enable register * (frm_pr16) these bits enable the errored events used to determine errored and severely errored seconds at the network termi- nation-1 interface. ntsa6-c, ntsa6-8, ntslip, ntais, ntlmfa, and ntlfa are the sa6-c, sa6-8, slip, ais, lmfa, and lfa errored events, respectively, as referred to the nt1 interface. a 1 in the bit position enables the cor- responding errored event. the default value of this register is 00 (hex). table 124. nt1 errored event enable register (frm_pr16) (y70) nt1 remote end errored event enable register * (frm_pr17frm_pr18) these bits enable the errored events used to determine errored and severely errored seconds at the network termi- nation-1 remote end interface. ntrerfa, ntreslip, ntreais, ntrelmfa, ntrelfa, ntresa6-c, ntresa6- f, ntresa6-e, and ntresa6-8 are the rfa, slip, ais, lmfa, lfa, sa6-c, sa6-f, sa6-e, and sa6-8 errored events, respectively, as referred to the nt-1 remote end interface. the default value of this register is 00 (hex). table 125. nt1 remote end errored event enable registers (frm_pr17frm_pr18) (y71y72) automatic ais to the system and automatic loopback enable register the default value of this register is 00 (hex). table 126. automatic ais to the system and automatic loopback enable register (frm_pr19) (y73) * one occurrence of any one of these events causes an errored second count increment and a severely errored second count increm ent. register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 frm_pr16 ntsa6-c 0 ntsa6-8 0 ntslip ntais ntlmfa ntlfa register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 frm_pr17 0 0 0 ntrerfa ntreslip ntreais ntrelmfa ntrelfa frm_pr18 0 0 0 0 ntresa6-c ntresa6-f ntresa6-e ntresa6-8 bit symbol description 0asais automatic s y stem ais. a 1 transmits ais to the s y stem whenever the receive framer is in the loss of receive frame ali g nment ( rlfa ) state. 1 asaistmx automatic s y stem ais cept crc-4 timer ex p iration. a 1 transmits ais to the s y s- tem after the crc-4 100 ms or 400 ms timer expires. ais is transmitted for the duration of the loss of crc-4 multiframe ali g nment state. 2 reserved. set to 0. 3tsais transmit s y stem ais. a 1 transmits ais to the s y stem. 4allbe automatic line loo p back enable. a 1 enables the framer section to execute the ds1 line loopback on or off commands without s y stem intervention. 5 reserved. set to 0. 6afdllbe automatic fdl line loo p back enable. a 1 enables the framer section to execute a line esf fdl loopback on or off command without s y stem intervention. 7 afdplbe automatic fdl pa y load loo p back enable. a 1 enables the framer section to execute a pa y load esf fdl loopback on or off command without s y stem intervention. preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 148 lucent technologies inc. lucent technologies inc. framer register architecture (continued) automatic ais to the system and automatic loopback enable register the default value of this register is 00 (hex). table 127. automatic ais to the system and automatic loopback enable register (frm_pr19) (y73) transmit test pattern to the line enable register * this register enables the transmit framer to transmit various test signals to the line interface. the default value of this register is 00 (hex). note that between enabling the transmission of line loopback on and off codes, this register must be set to 00 (hex) (i.e., to enable transmission of line loopback on code and then off code, write into this reg- ister 10 (hex), then 00 (hex), and finally 20 (hex)). table 128. transmit test pattern to the line enable register (frm_pr20) (y74 ) * to transmit test signals using this register, registers frm_pr69 and frm_pr70 must be set to 00 (hex). bit symbol description 0 asais automatic s y stem ais. a 1 transmits ais to the s y stem whenever the receive framer is in the loss of receive frame ali g nment ( rlfa ) state. 1asaistmx automatic s y stem ais cept crc-4 timer ex p iration. a 1 transmits ais to the s y s- tem after the crc-4 100 ms or 400 ms timer expires. ais is transmitted for the duration of the loss of crc-4 multiframe ali g nment state. 2 reserved. set to 0. 3tsais transmit s y stem ais. a 1 transmits ais to the s y stem. 4allbe automatic line loo p back enable. a 1 enables the framer section to execute the ds1 line loopback on or off commands without s y stem intervention. 5 reserved. set to 0. 6 afdllbe automatic fdl line loo p back enable. a 1 enables the framer section to execute a line esf fdl loopback on or off command without s y stem intervention. 7 afdplbe automatic fdl pa y load loo p back enable. a 1 enables the framer section to execute a pa y load esf fdl loopback on or off command without s y stem intervention. bit symbol description 0tufais unframed ais to line interface ( all ones pattern ) . 1 tufauxp unframed auxp to line interface in cept mode ( alternatin g 010101 unframed pattern ) . 2tprs transmit pseudorandom si g nal to line interface ( 2 15 C 1 ) . 3tqrs transmit quasi-random si g nal to line interface ( 2 20 C 1 ) ( ansi t1.403 ) . 4tllbon transmit framed pa y load line loo p back on code: 00001. 5tllboff transmit framed pa y load line loo p back off code: 001. 6tlic transmit line idle code of frm_pr22. when this bit = 1, the line idle code of frm_pr22 is transmitted to the line in all time slots . 7 ticrc transmit inverted crc. lucent technologies inc. 149 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. framer register architecture (continued) framer fdl control command register (frm_pr21) the default value of this register is 00 (hex). table 129. framer fdl control command register (frm_pr21) (y75) framer transmit line idle code register (frm_pr22) the value programmed in this register is transmitted as the line idle code. the default value is 7f (hex). table 130. framer transmit line idle code register (frm_pr22) (y76) framer system stuffed time-slot code register (frm_pr23) the value programmed in this register is transmitted in the stuffed time slots on the chi in the ds1 modes. the default value is 7f (hex). table 131. framer system stuffed time-slot code register (frm_pr23) (y77) bit symbol description 0 reserved. must be set to 0. 1 reserved. must be set to 0. 2 reserved. must be set to 0. 3 reserved. must be set to 0. 4 tfdllais transmit facilit y data link ais to the line. a 1 sends ais in the line side data link. 5 tfdlsais transmit facilit y data link ais to the s y stem. a 1 sends ais in the s y stem data link side. 6 tfdlc transmit fdl control bit. a 0 enables the transmission of the fdl bit from the internal fdl-hdlc unit ( default ) . a 1 enables the transmission of the fdl bit from the tfdl input or from the internal transmit stack dependin g on the state of frm_pr29 bit 5bit 7. when the slc -96 stack transmission is enabled ( re g ister frm_pr26 bit 5bit 7 = x10 ( binar y) , the fdl bit is sourced from the slc -96 transmit stack ( re g is- ter frm_pr31frm_pr35 ) . otherwise, it is sourced from tfdl. 7 tc/r=1 transmit esf_prm c/r = 1 ( tc/r = 1 ) . a 0 transmits the esf performance report mes- sa g e with the c/r bit = 0. ( see ansi t1.403-1995 for the prm structure and content. ) a 1 transmits the esf performance report messa g e with the c/r bit = 1. bit symbol description 07 tlic0tlic7 t ransmit line idle code 07. these 8 bits define the idle code transmitted to the line. bit symbol description 07 sstsc0 sstsc7 system stuffed time-slot code 07. these 8 bits define the idle code transmitted in the stuffed time slots to the s y stem chi. preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 150 lucent technologies inc. lucent technologies inc. framer register architecture (continued) primary loopback mode control and time slot address (frm_pr24) this register contains the loopback mode control and the 5-bit address of the line or system time slot to be looped back. the default value is 00 (hex) (no loopback). table 132. primary time-slot loopback address register (frm_pr24) (y78) table 133. loopback decoding of bits lbc[2:0] in frm_pr24, bits 75 bit symbol description 04 tslba0 tslba4 time-slot loopback address. 57 lbc0lbc2 loopback control bits[2:0]. lbc2 lbc1 lbc0 function 000 no loo p back. 001 line loo p back ( llb ) . the received line data is looped back to the transmit line data. 010 board loo p back ( blb ) . the received s y stem data is looped back to the transmit s y stem data and ais is sent as the line transmit data. 011 sin g le time-slot s y stem loo p back ( stsslb ) . s y stem chi loopback of the time slot selected b y bit 4bit 0. idle code selected b y frm_pr22 is inserted in the line pa y load in place of the looped back time slot. 100 sin g le time-slot line loo p back ( stsslb ) . line loopback of time slot selected b y bit 4bit 0. idle code selected b y frm_pr22 is inserted in the s y stem chi pa y load in place of the looped back time slot. 101 cept nailed-u p broadcast transmission ( cnubt ) . time slot selected b y bit 4bit 0 is transmitted normall y and also placed into time slot 0. 110 pa y load line loo p back with re g enerated framin g and crc bits. this mode is selected if frm_pr10 bit 3 = 0. the received channelized-pa y load data is looped backed to the line. the framin g bits are g enerated within the transmit framer. the re g enerated framin g information includes the f-bit pattern, the crc checksum bit, and the s y stems facilit y data link bit stream. this loopback mode can be used with the cept framin g mode. the entire time slot 0 data ( fas and not fas ) is re g ener- ated b y the transmit framer. the receive framer processes and monitors the incomin g line data normall y in this loopback mode and transmits the formatted data to the s y s- tem in the normal format via the chi. cept nailed-u p connect loo p back ( cnuclb ) . the received s y stem time slot selected b y this re g ister bit 4bit 0 is looped back to the s y stem in time slot 0. this mode is selected if frm_pr10 bit 3 = 1. 111 pa y load line loo p back with passthrou g h framin g and crc bits . the received channelized/pa y load data, the crc bits, and the frame ali g nment bits are looped back to the line. the s y stems facilit y data link bit stream is inserted into the looped back data and transmitted to the line. in esf, the fdl bits are i g nored when calculat- in g the crc-6 checksum. in cept, the fdl bits are included when calculatin g the crc-4 checksum, and as such this loopback mode g enerates crc-4 errors back at the remote end. lucent technologies inc. 151 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. framer register architecture (continued) secondary loopback control and id and address (frm_pr25) this register allows for a second single-time-slot loopback mode. this loopback is valid if the secondary time slot loopback address is different from the primary loopback address and the device is not in a line, board, or payload loopback, see frm_pr24. this register contains the secondary loopback mode control and the 5-bit address for the secondary line or system time slot to be looped back to the line or system. the default value is 00 (hex) (no loopback). table 134. secondary time-slot loopback address register (frm_pr25) (y79) table 135. loopback decoding of bits lbc[1:0] in frm_pr25, bits 65 bit symbol description 04 stsl ba0s tslba4 secondary time-slot loopback address. 56 slbc0slbc1 secondary loopback control bits[1:0]. 7 reserved. wri te to 0 . lbc1 lbc0 function 00 no loo p back. 01 secondar y sin g le time-slot s y stem loo p back. 10 secondar y sin g le time-slot line loo p back. 11 reserved. preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 152 lucent technologies inc. lucent technologies inc. framer register architecture (continued) framer reset and transparent mode control register (frm_pr26) the default value of this register is 00 (hex). table 136. framer reset and transparent mode control register (frm_pr26) (y7a) bits symbol description 0 swreset framer software reset. the framer and fdl sections are placed in the reset state for four clock c y cles of the frame internal line clock ( rfrmck ) . the parameter re g isters are forced to the default values. this bit is self-cleared. 1swrestart framer software restart. the framer and fdl sections are placed in the reset state as lon g as this bit is set to 1. the framers parameter re g isters are not chan g ed from their pro g rammed state. the fdl parameter re g isters are chan g ed from their pro g rammable state. this bit must be cleared. 2 frfrm framer reframe. a 0-to-1 transition of this bit forces the receive framer into the loss of frame ali g nment ( lfa ) state which forces a search of frame ali g nment. subse q uent reframe commands must have this bit in the 0 state first. 3 tfm1 trans p arent framin g mode 1. a 1 forces the transmit framer to pass s y stem data unmodified to the line and the receive framer to pass line data unmodified to the s y stem. the receive framer is forced not to ali g n to the input receive data. ds1: re g ister frm_pr43 bit 2bit 0 must be set to 000. the f bit is located in time slot 0, bit 7. the transmit framer extracts bit 7 of time slot 0 from rchidata and places this bit in the f-bit position of the transmit line data. the receive framer inserts the bit in the f-bit position of the receive line data into time slot 0, bit 7 of the tchidata. cept: rchidata time slot 0 is inserted into time slot 0 of the transmit line data. receive line time slot 0 is inserted into time slot 0 of tchidata. 4 tfm2 trans p arent framin g mode 2. a 1 forces the transmit framer to pass s y stem data unmodified to the line. the receive framer functions normall y as pro g rammed. ds1: re g ister frm_pr43 bit 2bit 0 must be set to 000. the f bit is located in time slot 0, bit 7. the transmit framer extracts bit 7 of time slot 0 from rchidata and places this bit in the f-bit position of the transmit line data. cept: rchidata time slot 0 is inserted into time slot 0 of the transmit line data. 5 sysfsm s y stem frame s y nc mask. a 1 masks the s y stem frame s y nchronization si g nal in the transmit framer section. note : the transmit framer must see at least one valid s y stem s y nchronization pulse to initialize its counts; afterwards, this bit ma y be set. for those applications that have j itter on the transmit clock si g nal relative to the s y stem clock si g nal, enable this bit so that the j itter is isolated from the transmit framer. 67 reserved. write to 0. lucent technologies inc. 153 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. framer register architecture (continued) automatic and manual transmission of the remote frame alarm control register (frm_pr27) the default value of this register is 00 (hex). table 137. transmission of remote frame alarm and cept automatic transmission of a bit = 1 control register (frm_pr27) (y7b) bit symbol description 0arlfa automatic remote frame alarm on lfa ( arlfa ) . a 1 transmits the remote frame alarm to the line whenever the receive framer detects loss of frame ali g nment ( rlfa ) . 1 aab16lmfa automatic a bit on lmfa ( cept onl y) . a 1 transmits a = 1 to the line whenever the receive framer detects loss of time slot 16 si g nalin g multiframe ali g nment ( rts16lmfa ) . 2 aab0lmfa automatic a bit on lmfa ( cept onl y) . a 1 transmits a = 1 to the line whenever the receive framer detects loss of time slot 0 multiframe ali g nment ( rts0lmfa ) . 3atmrx automatic a bit on crc-4 multiframe reframer timer ex p iration ( cept onl y) . a 1 transmits a = 1 to the line when the receive framer detects the expiration of either the 100 ms or 400 ms timers due to loss of multiframe ali g nment. 4 aarsa6_8 automatic a bit on rsa6_8 ( cept onl y) . a 1 transmits a = 1 to the line whenever the receive framer detects the sa6 = 1000 pattern. 5 aarsa6_c automatic a bit on rsa6_c ( cept onl y) . a 1 transmits a = 1 to the line whenever the receive framer detects the sa6 = 1100 pattern. 6tjrfa transmit d4 ja p anese remote frame alarm. a 1 transmits a valid japanese remote frame alarm for the d4 frame format. 7trfa transmit remote frame alarm. a 1 transmits a valid remote frame alarm for the corre- spondin g frame format. preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 154 lucent technologies inc. lucent technologies inc. framer register architecture (continued) automatic and manual transmission of e bit = 0 control register the default value of this register is 00 (hex). table 138. cept automatic transmission of e bit = 0 control register (frm_pr28) (y7c) * whenever bits (e.g., si, sa, etc.) are transmitted from the system transparently, frm_pr29 must first be momentarily written to 001xxxxx (binary). otherwise, the transmit framer will not be able to locate the biframe alignment. sa4sa8 source register (frm_pr29) these bits contain the fixed transmit sa bits and define the source of the sa bits. the default value of this register is 00 (hex). table 139. sa4sa8 source register (frm_pr29) (y7d) bit symbol description 0 sis, si-bit source. in cept with no crc-4 mode, a 1 transmits tsif and tsinf in the si bit position to the line in fas and not fas, respectivel y . a 0, in non-crc-4 mode, trans- mits s y stem si data to the line transparentl y *. t1e transmit one e = 0. in cept with crc-4 mode, a 0 transmits e = tsif in frame 13 and e = tsinf in frame 15. a 1 transmits one e bit = 0 for each write access to tsif = 0 or tsinf = 0. 1tsif transmit bit 1 in fas. in cept with no crc-4, this bit can be transmitted to the line in bit 1 of the fas. in crc-4 mode, this bit is used for e-bit data in frame 13. 2tsinf transmit bit 1 in not fas. in cept with no crc-4, this bit can be transmitted to the line in bit 1 of the not fas. in crc-4 mode, this bit is used for e-bit data in frame 15. 3 atercrce automatic transmit e bit = 0 for received crc-4 errored events. a 1 transmits e = 0 to the line whenever the receive framer detects a crc-4 errored checksum. 4 atelts0mfa automatic transmit e bit = 0 for received loss of crc-4 multiframe ali g nment. a 1 transmits e = 0 to the line whenever the receive framer detects a loss of crc-4 multi- frame ali g nment condition. 5atertx automatic transmit e bit = 0 on ex p iration of cept crc-4 loss of multiframe timer. a 1 transmits e = 0 to the line whenever the receive framer detects the expiration of either the 100 ms or 400 ms timer due to the loss of crc-4 multiframe ali g nment. 67 these bits are zero. bit symbol description 04 tsa4tsa8 transmit sa4sa8 bit. 57 sas5sas7 sa source control bits[2:0]. lucent technologies inc. 155 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. framer register architecture (continued) table 140. sa bits source control for bit 5bit 7 in frm_pr29 * whenever bits (e.g., si, sa, etc.) are transmitted from the system transparently, frm_pr29 must first be momentarily written t o 001xxxxx (binary). otherwise, the transmit framer will not be able to locate the biframe alignment. sa4sa8 control register (frm_pr30) in conjunction with frm_pr29 bit 5bit 7, these bits define the source of the individual sa4sa8 bits. the default value of this register is 00 (hex). table 141. sa4sa8 control register (frm_pr30) (y7e) sas7 sas6 sas5 function 100a sin g le sa bit, selected in re g ister frm_pr43, is sourced from either the external transmit facilit y data input port tfdl ( frm_pr21 bit 6 = 1 ) or from the internal fdl- hdlc block ( frm_pr21 bit 6 = 0 ) . the remainin g sa bits are sourced b y this re g ister bit 0bit 4 if enabled in re g ister frm_pr30, or transparentl y from the s y stem inter- face*. 101a sin g le sa bit, selected in re g ister frm_pr43, is sourced from either the external transmit facilit y data input port tfdl ( frm_pr21 bit 6 = 1 ) or from the internal fdl- hdlc block ( frm_pr21 bit 6 = 0 ) . the remainin g sa bits are transmitted transpar- entl y from the s y stem interface*. 11xa sin g le sa bit, selected in re g ister frm_pr43, is sourced from either the external transmit facilit y data input port tfdl ( frm_pr21 bit 6 = 1 ) or from the internal fdl- hdlc block ( frm_pr21 bit 6 = 0 ) . the remainin g sa bits are sourced from the trans- mit sa stack re g isters ( frm_pr31frm_pr40 ) if enabled in re g ister frm_pr30, or transparentl y from the s y stem interface*. 01x slc -96 mode. transmit slc -96 stack and the slc -96 interrupts are enabled. the slc -96 fdl bits are sourced from the transmit slc -96 stack, re g isters frm_pr31 frm_pr40. cept mode. transmit sa stack and the sa interrupts are enabled. the sa bits are sourced from the transmit sa stack ( frm_pr31frm_pr40 ) if enabled in re g ister frm_pr30, or transparentl y from the s y stem interface*. 001sa [ 4:8 ] bits are transmitted from the s y stem interface transparentl y throu g h the framer*. 000sa [ 4:8 ] bits are sourced b y bit 0bit 4 of this re g ister if enabled in re g ister frm_pr30, or transparentl y from the s y stem interface*. bit symbol description 04 tesa4tesa8 trans p arent enable sa4sa8 bit mask. a 1 enables the transmission of the cor- respondin g sa bits from the sa source re g ister ( frm_pr29 bit 0bit 4 ) or from the transmit sa stack. a 0 allows the correspondin g sa bit to be transmitted transpar- entl y from the s y stem interface. 56 reserved. write to 0. 7tdnf transmit double not fas s y stem time slot. a 0 enables the transmission of the fas and not fas on the tchidata interface. a 1 enables the not fas to be transmitted twice on the tchidata interface, and the received time slot 0 from the rchidata is assumed to carr y not fas data that is repeated twice. preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 156 lucent technologies inc. lucent technologies inc. framer register architecture (continued) sa transmit stack register (frm_pr31frm_pr40) in cept frame format, registers frm_pr31frm_pr40 are used to program the sa bits in the cept multiframe not-fas words. if crc-4 is enabled, this data is transmitted to the line synchronously to the crc-4 multiframe. the default value of these registers is 00 (hex). table 142. sa transmit stack (frm_pr31frm_pr40) (y7fy88) slc -96 transmit stack (frm_pr31frm_pr40) in slc -96 frame format, registers frm_pr31frm_pr35 are used to source the transmit facility data link bits in the f s bit positions. the default value of these registers is 00 (hex). table 143 . slc -96 transmit stack (frm_pr31frm_pr40) (y7fy88) in slc -96 frame format, the bits in registers frm_pr31frm_pr35 are transmitted using the format shown in table 144. table 144. transmit slc -96 fdl format register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 frm_pr31 sa4-1 sa4-3 sa4-5 sa4-7 sa4-9 sa4-11 sa4-13 sa4-15 frm_pr32 sa4-17 sa4-19 sa4-21 sa4-23 sa4-25 sa4-27 sa4-29 sa4-31 frm_pr33 sa5-1 sa5-3 sa5-5 sa5-7 sa5-9 sa5-11 sa5-13 sa5-15 frm_pr34 sa5-17 sa5-19 sa5-21 sa5-23 sa5-25 sa5-27 sa5-29 sa5-31 frm_pr35 sa6-1 sa6-3 sa6-5 sa6-7 sa6-9 sa6-11 sa6-13 sa6-15 frm_pr36 sa6-17 sa6-19 sa6-21 sa6-23 sa6-25 sa6-27 sa6-29 sa6-31 frm_pr37 sa7-1 sa7-3 sa7-5 sa7-7 sa7-9 sa7-11 sa7-13 sa7-15 frm_pr38 sa7-17 sa7-19 sa7-21 sa7-23 sa7-25 sa7-27 sa7-29 sa7-31 frm_pr39 sa8-1 sa8-3 sa8-5 sa8-7 sa8-9 sa8-11 sa8-13 sa8-15 frm_pr40 sa8-17 sa8-19 sa8-21 sa8-23 sa8-25 sa8-27 sa8-29 sa8-31 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 frm_pr31 0 0 x-0 x-0 x-0 x-1 x-1 x-1 frm_pr32 0 0 x-0 x-0 x-0 x-1 x-1 x-1 frm_pr33 xc 1 xc 2 xc 3 xc 4 xc 5 xc 6 xc 7 xc 8 frm_pr34 xc 9 xc 10 xc 11 xspb 1 = 0 xspb 2 = 1 xspb 3 = 0 xm 1 xm 2 frm_pr35 xm 3 xa 1 xa 2 xs 1 xs 2 xs 3 xs 4 xspb 4 = 1 frm_pr36 frm_pr40 00 000000 fs= 000111000111 xc 1 xc 2 xc 3 xc 4 xc 5 xc 6 xc 7 xc 8 xc 9 xc 10 xc11 xspb1 xspb2 xspb3 xm1 xm2 xm3 xa1 xa2 xs1 xs2 xs3 xs4 xspb4 lucent technologies inc. 157 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. framer register architecture (continued) cept time slot 16 x-bit remote multiframe alarm and ais control register (frm_pr41) the default value of this register is 00 (hex). table 145. cept time slot 16 x-bit remote multiframe alarm and ais control register (frm_pr41) (y89) framer exercise register (frm_pr42) this register is used for exercising the device in test mode. setting the framer exercise bits 05 as described in table 146 causes the specified error condition to be generated. in normal operation, it should be set to 00 (hex). the default value of this register is 00 (hex). table 146. framer exercise register (frm_pr42) (y8a) bit symbol description 02 tts16x0tts16x2 transmit time slot 16 x0x2 bits. the content of these bits are written into cept si g nalin g multiframe time slot 16 x bits. 3xs x-bit source. a 1 enables the tts16x [ 2:0 ] bits to be written into cept time slot 16 si g nalin g multiframe frame. a 0 transmits the x bits transparentl y . 4 altts16rmfa automatic line transmit time slot 16 remote multiframe alarm. a 1 enables the transmission of cept time slot 16 si g nalin g remote multiframe alarm when the receive framer is in the loss of cept si g nalin g ( rts16lmfa ) state. 5 tlts16rmfa transmit line time slot 16 remote multiframe alarm. a 1 enables the trans- mission of cept time slot 16 si g nalin g remote multiframe alarm. 6tlts16ais transmit line time slot 16 ais. a 1 enables the transmission of cept time slot 16 alarm indication si g nal. 7 reserved. write to 0. bit description fex0fex5 framer exercise bits 05 ( fex0fex5 ) . see table 147. fex6 fex7 pulse wide interval. 001 s pulse. 0 1 500 ms pulse. 1 0 100 ms pulse. 11reserved. preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 158 lucent technologies inc. lucent technologies inc. framer register architecture (continued) table 147. framer exercises, frm_pr42 bit 5bit 0 (y8a) exercise type fex5 fex4 fex3 fex2 fex1 fex0 exercise framing format facilit y status 0 0 1 0 0 0 line format violation. all crc checksum error. esf or cept receive remote frame alarm. d4 or esf 0 0 1 0 0 1 alarm indication si g nal detection. all loss of frame ali g nment. cept receive remote frame alarm. japanese d4 0 0 1 0 1 0 time slot 0 1-bit shift. cept transmit corrupt crc. esf & cept 0 0 1 0 1 1 frame-bit error & loss of frame ali g nment. all loss of time slot 16 multiframe ali g nment. cept remote frame alarm. d4 & dds crc bit errors. esf & cept 0011 00frame-bit errors. all 0 0 1 1 0 1 frame-bit errors & loss of frame ali g nment. all loss of time slot 16 multiframe ali g nment. cept 0 0 1 1 1 0 frame-bit error & loss of frame ali g nment. all chan g e of frame ali g nment. esf, dds, & cept loss of time slot 16 multiframe ali g nment. cept 0 0 1 1 1 1 excessive crc checksum errors. esf & cept 0 0 0 0 0 0 no test mode activated. lucent technologies inc. 159 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. framer register architecture (continued) table 147. framer exercises, frm_pr42 bit 5bit 0 (y8a) (continued) ds1 system interface control and cept fdl source control register (frm_pr43) the default value of this register is 00 (hex). table 148. ds1 system interface control and cept fdl source control register (frm_pr43) (y8b) exercise type fex5 fex4 fex3 fex2 fex1 fex0 exercise framing format performance status 0 1 0 0 0 0 errored second all 010 0 0 1burst y errored second 0 1 0 0 1 0 severel y errored second 0 1 0 0 1 1 severel y errored second count 0 1 0 1 0 0 unavailable state 010 1 0 1factor y test 0 1 0 1 1 0 increment status counters sr6sr14 0 1 0 1 1 1 increment status counters sr6sr14 status counters 1 0 0 0 0 1 crc error counter all 1 0 0 0 1 0 errored event counter 1 0 x 0 1 1 errored second counter 1 0 0 1 0 0 severel y errored second counter 1 0 0 1 0 1 unavailable second counter 1 0 0 1 1 0 line format violation counter 1 0 0 1 1 1 frame bit error counter all other combinations reserved bit symbol description 02 sts0sts2 in ds1 mode, bit 0bit 2 pro g ram the positions of the stuffed time slots on the chi. the content of the stuffed time slot can be pro g rammed usin g re g ister frm_pr23. bits 210 000 = sdddsdddsdddsdddsdddsdddsdddsddd 001 = dsdddsdddsdddsdddsdddsdddsdddsdd 010 = ddsdddsdddsdddsdddsdddsdddsdddsd 011 = dddsdddsdddsdddsdddsdddsdddsddds 100 = ddddddddddddddddddddddddssssssss safdl0 safdl2 in cept mode, bit 0bit 2 pro g ram the sa-bit source of the facilit y data link. bits 210 000: sa4 = fdl 001: sa5 = fdl 010: sa6 = fdl 011: sa7 = fdl 100: sa8 = fdl in both ds1 and cept modes, onl y the bit values shown above ma y be selected. 3ssc slc -96 si g nalin g control ( ds1 onl y) . a 1 enables the slc -96 9-state si g nalin g mode. a 0 enables 16-state si g nalin g in the slc -96 framin g mode. 47 reserved. write to 0. preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 160 lucent technologies inc. lucent technologies inc. framer register architecture (continued) signaling mode register (frm_pr44) this register programs various signaling modes. the default value is 00 (hex). table 149. signaling mode register (frm_pr44) (y8c) bit symbol description 0tsig trans p arent si g nalin g . a 0 enables signaling information to be inserted into and extracted from the data stream. the signaling source is either the signaling registers or the system data (in the associated signaling mode). in ds1 modes, the choice of data or voice channels assignment for each channel is a function of the programming of the f and g bits in the transmit signaling registers. a 1 enables data to pass through the device transparently. all channels are treated as data channels. 1stomp stom p mode. a 0 allows the received signaling bits to pass through the receive signal- ing circuit unmodified. in ds1 robbed-bit signaling modes, a 1 enables the receive sig- naling circuit to replace (in those time slots programmed for signaling) all signaling bits (in the receive line bit stream) with a 1, after extracting the valid signaling information. in cept time slot 16 signaling modes, a 1 enables the received signaling circuit substitute of the signaling combination of abcd = 0000 to abcd = 1111. 2asm associated si g nalin g mode. a 1 enables the associate signaling mode which config- ures the chi to carry both data and its associated signaling information. enabling this mode must be in conjunction with the programming of the chi data rate to 4.096 mbits/s or 8.192 mbit/s. each channel consists of 16 bits where 8 bits are data and the remaining 8 bits are signaling information. 3rsi receive si g nalin g inhibit. a 1 inhibits updatin g of the receive si g nalin g buffer. 4mos messa g e-oriented si g nalin g . ds1: a 1 enables the channel 24 message-oriented signaling mode. 5 tsr-asm tsr-asm mode ( ds1 onl y) . in the ds1 mode, settin g this bit and frm_pr44 bit 2 ( asm ) to 1 enables the transmit si g nalin g re g ister f and g bits to define the robbed-bit si g nalin g format while the abcd bit information is extracted from the chi interface. the f and g bits are copied to the receive si g nalin g block and are used to extract the si g nal- in g information from the receive line. 6astsais automatic s y stem transmit si g nalin g ais ( cept onl y) . a 1 transmits ais in s y stem time slot 16 durin g receive loss of time slot 16 si g nalin g multiframe ali g nment state. 7tcss transmit cept s y stem si g nalin g s q uelch ( cept onl y) . ais is transmitted in time slot 16 of the transmit s y stem data. lucent technologies inc. 161 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. framer register architecture (continued) chi common control register (frm_pr45) these bits define the common attributes of the chi for tchidata, tchidatab, rchidata, and rchdatab. the default value of this register is 00 (hex). table 150. chi common control register (frm_pr45) (y8d) bit symbol description 0hflf hi g h-fre q uenc y /low-fre q uenc y pllck clock mode. a 0 enables the low-fre q uenc y pllck mode for the divide-down circuit in the internal phase-lock loop section ( ds1 pllck = 1.544 mhz; cept pllck = 2.048 mhz ) . the divide-down circuit will produce an 8 khz si g nal on div-pllck, pin g25. a 1 enables the hi g h-fre q uenc y pllck mode for the divide-down circuit in the internal phase-lock loop section ( ds1: pllck = 6.176 ( 4 x 1.544 ) mhz; cept: 8.192 ( 4 x 2.048 ) mhz ) . the divide-down circuit will produce a 32 khz si g nal on div-pllck. 1cms concentration hi g hwa y clock mode. a 0 enables the chi clock fre q uenc y and chi data rate to be e q ual. function of cms = 1 is reserved. this control bit affects both the transmit and receive interfaces. 23 cdrs0 cdrs1 concentration hi g hwa y interface data rate select. bits chi data rate 23 0 0 2.048 mbits/s 0 1 4.096 mbits/s 1 0 8.192 mbits/s 11 reserved 4chimm concentration hi g hwa y master mode. a 0 enables external s y stems frame s y nchroni- zation si g nal ( chifs ) to drive the transmit path of the framers concentration hi g hwa y interface. a 1 enables the framers transmit concentration interface to g enerate a s y stem frame s y nchronization si g nal derived from the receive line interface. the framers s y stem frame s y nchronization si g nal is g enerated on the chifs output pin. applications usin g the receive line clock as the reference clock si g nal of the s y stem are recommended to enable this mode and use the chifs si g nal g enerated b y the framer. the receive chi path is not affected b y this mode. 56 reserved. write to 0. 7 hwyen hi g hwa y enable. a 1 in this bit position enables transmission to the concentration hi g h- wa y . this allows the TFRA08C13 to be full y confi g ured before transmission to the hi g h- wa y . a 0 forces the idle code as defined in re g ister frm_pr22 to be transmitted to the line in all pa y load time slots and the transmit chi pin is forced to a hi g h-impedance state for all chi transmitted time slots. preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 162 lucent technologies inc. lucent technologies inc. framer register architecture (continued) chi common control register (frm_pr46) this register defines the common attributes of the transmit and receive chi. the default value is 00 (hex). table 151. chi common control register (frm_pr46) (y8e) chi transmit control register (frm_pr47) the default value of this register is 00 (hex). table 152. chi transmit control register (frm_pr47) (y8f) chi receive control register (frm_pr48) the default value of this register is 00 (hex). table 153. chi receive control register (frm_pr48) (y90) bit symbol description 02 toff0 toff2 transmit chi bit offset. these 3 bits define the bit offset from chifs for each transmit time slot. the offset is the number of chick clock periods b y which the first bit is dela y ed from tchifs. 3tfe transmit frame clock ed g e. a 0 ( 1 ) enables the fallin g ( risin g) ed g e of chick to latch in the frame s y nchronization si g nal, chifs. 46 roff0 roff2 receive chi bit offset. these 3 bits define the bit offset from chifs for each received time slot. the offset is the number of chick clock periods b y which the first bit is dela y ed from rchifs. 7rfe received frame clock ed g e. a 0 ( 1 ) enables the fallin g ( risin g) ed g e of chick to latch in the frame s y nchronization si g nal, chifs. bit symbol description 05 tbyoff0 tbyoff5 transmit b y te offset. combined with frm_pr65 bit 0 ( tbyoff6 ) , these 6 bits define the b y te offset from chifs to the be g innin g of the next transmit chi frame on tchidata. 6tce transmitter clock ed g e. a 1 ( 0 ) enables the risin g ( fallin g) ed g e of chick to clock out data on tchidata. 7 reserved. write to 0 bit symbol description 05 rbyoff0 rbyoff5 receiver b y te offset. combined with frm_pr66 bit 0 ( rbyoff6 ) , these 6 bits define the b y te offset from chifs to the be g innin g of the next receive chi frame on rchidata. 6 rce receiver clock ed g e. a 1 ( 0 ) enables the risin g ( fallin g) ed g e of chick to latch data on rchidata. 7 reserved. write to 0 lucent technologies inc. 163 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. framer register architecture (continued) chi transmit time-slot enable registers (frm_pr49frm_pr52) these four registers define which transmit chi time slots are enabled. a 1 enables the tchidata or tchidatab time slot. a 0 forces the chi transmit highway time slot to be 3-stated. the default value of this register is 00 (hex). table 154. chi transmit time-slot enable registers (frm_pr49frm_pr52) (y91y94) chi receive time-slot enable registers (frm_pr53frm_pr56) these four registers define which receive chi time slots are enabled. a 1 enables the rchidata or rchidatab time slots. a 0 disables the time slot and transmits the programmable idle code of register frm_pr22 to the line in the corresponding time slot. the default value of this register is ff (hex). table 155. chi receive time-slot enable registers (frm_pr53frm_pr56) (y95y98) chi transmit highway select registers (frm_pr57frm_pr60) these four registers define which transmit chi highway tchidata or tchidatab contains valid data for the active time slot. a 0 enables tchidata, and a 1 enables tchidatab. the default value of this register is 00 (hex). table 156. chi transmit highway select registers (frm_pr57frm_pr60) (y99y9c) chi receive highway select registers (frm_pr61frm_pr64) these four registers define which receive chi highway rchidata or rchidatab contains valid data for the active time slot. a 0 enables rchidata and a 1 enables rchidatab. the default value of these registers is 00 (hex). table 157. chi receive highway select registers (frm_pr61frm_pr64) (y9dya0) register bit symbol description frm_pr49 70 ttse31ttse24 transmit time-slot enable bits 3124. frm_pr50 70 ttse23ttse16 transmit time-slot enable bits 2316. frm_pr51 70 ttse15ttse8 transmit time-slot enable bits 158. frm_pr52 70 ttse7ttse0 transmit time-slot enable bits 70. register bit symbol description frm_pr53 70 rtse31rtse24 receive time-slot enable bits 3124. frm_pr54 70 rtse23rtse16 receive time-slot enable bits 2316. frm_pr55 70 rtse15rtse8 receive time-slot enable bits 158. frm_pr56 70 rtse7rtse0 receive time-slot enable bits 70. register bit symbol description frm_pr57 70 ths31ths24 transmit highway select bits 3124. frm_pr58 70 ths23ths16 transmit highway select bits 2316. frm_pr59 70 ths15ths8 transmit highway select bits 158. frm_pr60 70 ths7ths0 transmit highway select bits 70. register bit symbol description frm_pr61 70 rhs31rhs24 receive highway select bits 3124. frm_pr62 70 rhs23rhs16 receive highway select bits 2316. frm_pr63 70 rhs15rhs8 receive highway select bits 158. frm_pr64 70 rhs7rhs0 receive highway select bits 70. preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 164 lucent technologies inc. lucent technologies inc. framer register architecture (continued) chi transmit control register (frm_pr65) the default value of this register is 00 (hex). table 158. chi transmit control register (frm_pr65) (ya1) chi receive control register (frm_pr66) the default value of this register is 00 (hex). table 159. chi receive control register (frm_pr66) (ya2) bit symbol description 0 tbyoff6 transmit chi 64-b y te offset. a 1 enables a 64-b y te offset from chifs to the be g innin g of the next transmit chi frame on tchidata. a 0 enables a 0-b y te offset ( if bit 0bit 5 of frm_pr47 = 0 ) . combin g bit 0bit 5 of frm_pr47 with this bit allows pro g rammin g the b y te offset from 0127. 1 tchidts transmit chi double time-slot mode. a 1 enables the transmit chi double time-slot mode. in this mode, the chi clock runs at twice the rate of tchidata. 27 reserved. write to 0. bit symbol description 0 rbyoff6 receive chi 64-byte offset. a 1 enables a 64-b y te offset from chifs to the be g innin g of the next receive chi frame on rchidata. a 0 enables a 0-b y te offset ( if bit 0 bit 5 of frm_pr48 = 0 ) . combin g bit 0bit 5 of frm_pr48 with this bit allows pro g ram- min g the b y te offset from 0127. 1 rchidts receive chi double time-slot mode. a 1 enables the transmit chi double time-slot mode. in this mode, the chi clock runs at twice the rate of rchidata. 27 reserved. write to 0. lucent technologies inc. 165 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. framer register architecture (continued) reserved parameter/control registers registers frm_pr67 and frm_pr68, addresses 6a3 and 6a4 or ca3 and ca4, are reserved. write these regis- ters to 0. auxiliary pattern generator control register (frm_pr69) the following register programs the auxiliary pattern generator in the transmit framer. the default value of this reg- ister is 00 (hex). table 160. auxiliary pattern generator control register (frm_pr69) (ya5) * * to generate test pattern signals using this register, register frm_pr20 must be set to 00 (hex). bit symbol description 0itd invert transmit data. settin g this bit to 1 inverts the transmitted pattern. 1 tpei test pattern error insertion. to gg lin g this bit from a 0 to a 1 inserts a sin g le bit error in the transmitted test pattern. 2 gblksel generator block select. settin g this bit to 1 enables the g eneration of test patterns in this re g ister. 3 gfrmsel generator frame test pattern. settin g this bit to 1 results in the g eneration of an unframed pattern. a 0 results in a framed pattern ( t1 and cept ) . 47 gptrn0 gptrn3 generator pattern select. these 4 bits select which random pattern is to be transmitted. bits 7654 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 description mark ( all ones ) ( ais ) qrss ( 2 20 C 1 with zero suppression ) 2 5 C 1 63 ( 2 6 C 1 ) 511 ( 2 9 C 1 ) 511 ( 2 9 C 1 ) reversed 2047 ( 2 11 C 1 ) 2047 ( 2 11 C 1 ) reversed 2 15 C 1 2 20 C 1 2 20 C 1 2 23 C 1 1:1 ( alternatin g) generator polynomial 1+x C17 +x C20 1+x C3 +x C5 1+x C1 +x C6 1+x C5 +x C9 1+x C4 +x C9 1+x C9 +x C11 1+x C2 x C11 1+x C14 +x C15 1+x C3 +x C20 1+x C17 +x C20 1+x C18 +x C23 standard o.151 o.153 o.152 o.151 o.153 cb113/cb114 o.151 preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 166 lucent technologies inc. lucent technologies inc. framer register architecture (continued) pattern detector control register (frm_pr70) the following register programs the pattern detector in the receive framer. the default value of this register is 00 (hex). this register must be set to 00 (hex) before a pattern is selected or changed. this register must be set to 00 (hex) to clean register frm_sr7. once a selected pattern is detected, the detector remains locked to that align- ment and all differences from the expected are reported an bit errors. pattern-realignment can only occur following a reset of this register, setting it to 00 (hex). table 161. pattern detector control register (frm_pr70) (ya6) * * to generate/detect test pattern signals using this register, register frm_pr20 must be set to 00 (hex). bit symbol description 0ird invert receive data. settin g this bit to 1 enables the pattern detector to detect the inverse of the selected pattern. 1 reserved. write to 0. 2 dblksel detector block select. settin g this bit to 1 enables the detection of test patterns in this re g ister. 3duftp detect unframed test pattern. settin g this bit to 1 results in the search for an unframed pattern. a 0 results in a search for a framed pattern ( t1 and cept ) . 47 dptrn0 dptrn3 detector pattern select. these 4 bits select which random pattern is to be detected . bits 7654 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 description mark ( all ones ) ( ais ) qrss ( 2 20 C 1 with zero suppression ) 2 5 C 1 63 ( 2 6 C 1 ) 511 ( 2 9 C 1 ) 511 ( 2 9 C 1 ) reversed 2047 ( 2 11 C 1 ) 2047 ( 2 11 C 1 ) reversed 2 15 C 1 2 20 C 1 2 20 C 1 2 23 C 1 1:1 ( alternatin g) generator polynomial 1+x C17 +x C20 1+x C3 +x C5 1+x C1 +x C6 1+x C5 +x C9 1+x C4 +x C9 1+x C9 +x C11 1+x C2 x C11 1+x C14 +x C15 1+x C3 +x C20 1+x C17 +x C20 1+x C18 +x C23 standard o.151 o.153 o.152 o.151 o.153 cb113/cb114 o.151 lucent technologies inc. 167 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. framer register architecture (continued) transmit signaling registers: ds1 format (frm_tsr0frm_tsr23) these registers program the transmit signaling registers for the ds1 and cept mode. the default value of these registers is 00 (hex). table 162. transmit signaling registers: ds1 format (frm_tsr0frm_tsr23) (ye0yf7) transmit signaling registers: cept format (frm_tsr0frm_tsr31) table 163. transmit signaling registers: cept format (frm_tsr0frm_tsr31) (ye0yff) * in pcs0 or pcs1 signaling mode, this bit is undefined. transmit signal registers bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ds1 transmit si g nalin g re g isters ( 023 ) pgfxdcba esf format: voice channel with 16-state si g nalin g slc -96: 9-state si g nalin g ( dependin g on the settin g in re g ister frm_pr43 ) x00xdcba voice channel with 4-state si g nalin g x0 1xxxba voice channel with 2-state si g nalin g x1 1xxxaa data channel ( no si g nalin g) x1 0xxxxx transmit signal registers bit 7 bit 65 bit 4 * bit 3 bit 2 bit 1 bit 0 frm_tsr1frm_tsr15 p x e [ 1:15 ] d [ 1:15 ] c [ 1:15 ] b [ 1:15 ] a [ 1:15 ] frm_tsr17frm_tsr31 p x e [ 17:31 ] d [ 17:31 ] c [ 17:31 ] b [ 17:31 ] a [ 17:31 ] preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 168 lucent technologies inc. lucent technologies inc. fdl register architecture regbank9regbank12 contain the status and programmable control registers for the facility data link chan- nels fdl1fdl8, respectively. the base address for regbank9 is a00 (hex), regbank10 is b00 (hex), regbank11 is c00 (hex), and for regbank12 is d00 (hex). within these register banks, the bit map is identical for fdl1fdl8. the register bank architecture for fdl1fdl8 is shown in table 164. the register bank consists of 8-bit registers classified as either (programmable) parameter registers or status registers. default values are shown in parenthe- ses. table 164. fdl register set ((a00a0e); (a20a2e); (b00b0e); (b20b2e) (c00c0e); (c20c2e); (d00d0e); (d20d2e)) * for fdl 1 and fdl 2, y = a; for fdl 3 and fdl 4, y = b; for fdl 5 and fdl 6, y = c; for fdl 7 and fdl 8, y = d. fdl register register address * (hexadecimal) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 fdl 1 fdl 3 fdl 5 fdl 7 fdl 2 fdl 4 fdl 6 fdl 8 fdl_pr0 y00 y20 fransit3 (1) fransit2 (0) fransit1 (1) fransit0 (0) reserved (0) reserved (0) flags (0) fdint (0) fdl_pr1 y01 y21 ftprm (0) frpf (0) ftr (0) frr (0) fte (0) fre (0) fllb (0) frlb (0) fdl_pr2 y02 y22 ftbcrc (0) friie (0) frovie (0) freofie (0) frfie (0) ftundie (0) fteie (0) ftdie (0) fdl_pr3 y03 y23 ftfc (0) ftabt (0) ftil5 (0) ftil4 (0) ftil3 (0) ftil2 (0) ftil1 (0) ftil0 (0) fdl_pr4 y04 y24 ftd7 (0) ftd6 (0) ftd5 (0) ftd4 (0) ftd3 (0) ftd2 (0) ftd1 (0) ftd0 (0) fdl_pr5 y05 y25 ftic7 (0) ftic6 (0) ftic5 (0) ftic4 (0) ftic3 (0) ftic2 (0) ftic1 (0) ftic0 (0) fdl_pr6 y06 y26 fransie (0) afdlbpm (0) fril5 (0) fril4 (0) fril3 (0) fril2 (0) fril1 (0) fril0 (0) fdl_pr8 y08 y28 frmc7 ( 0 ) frmc6 ( 0 ) frmc5 ( 0 ) frmc4 ( 0 ) frmc3 ( 0 ) frmc2 ( 0 ) frmc1 ( 0 ) frmc0 ( 0 ) fdl_pr9 y09 y29 reserved ( 0 ) ftm ( 0 ) fmatch ( 0 ) faloct ( 0 ) fmstat ( 0 ) foctof2 ( 0 ) foctof1 ( 0 ) foctof0 ( 0 ) fdl_pr10 y0a y2a ftansi ( 0 ) reserved ( 0 ) ftansi5 ( 0 ) ftansi4 ( 0 ) ftansi3 ( 0 ) ftansi2 ( 0 ) ftansi1 ( 0 ) ftansi0 ( 0 ) fdl_sr0 y0b y2b fransi fridl froverun freof frf ftundabt ftem ftdone fdl_sr1 y0c y2c fted ftqs6 ftqs5 ftqs4 ftqs3 ftqs2 ftqs1 ftqs0 fdl_sr2 y0d y2d freof frqs6 frqs5 frqs4 frqs3 frqs2 frqs1 frqs0 fdl_sr3 y0e y2e 0 0 x5 x4 x3 x2 x1 x0 fdl_sr4 y07 y27 frd7 frd6 frd5 frd4 frd3 frd2 frd1 frd0 lucent technologies inc. 169 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. fdl parameter/control registers ((a00a0e); (a20a2e); (b00b0e); (b20b2e) (c00c0e); (c20c2e); (d00d0e); (d20d2e)) these registers define the mode configuration of each framer unit. these registers are initially set to a default value upon a hardware reset. these registers are all read/write registers. default states of all bits in this register group are also indicated in the parameter/control register map. table 165. fdl configuration control register (fdl_pr0) (a00; a20; b00; b20; c00; c20; d00; d20) * the fransit bits (fdl_pr0 bits 47) must be changed only following an fdl reset or when the fdl is idle. table 166. fdl control register (fdl_pr1) (a01; a21; b01; b21; c01; c21; d01; d21) bit symbol description 0 fdint d y namic interru p t. fdint = 0 causes multiple occurrences of the same event to g ener- ate a sin g le interrupt before the interrupt bit is cleared b y readin g re g ister fdl_sr0. fdint = 1 causes multiple interrupts to be g enerated. this bit should normall y be set to 0. 1flags fla g s. flags = 0 forces the transmission of the idle pattern ( 11111111 ) in the absence of transmit fdl information. flags = 1 forces the transmission of the fla g pattern ( 01111110 ) in the absence of transmit fdl information. this bit resets to 0. 23 reserved. write to 0. 47 fransit0 fransit3 receive ansi bit code threshold. these bits define the number of esf ansi bit codes needed for indicatin g a valid code. the default is ten ( 1010 ( binar y)) *. bit symbol description 0frlb remote loo p back. frlb = 1 loops the received facilit y data back to the transmit facilit y data interface. this bit resets to 0. 1 fllb local loo p back. fllb = 1 loops transmit facilit y data back to the receive facilit y data link interface. the receive facilit y data link information from the framer interface is i g nored. this bit resets to 0. 2fre fdl receiver enable. fre = 1 activates the fdl receiver. fre = 0 forces the fdl receiver into an inactive state. this bit resets to 0. 3fte fdl transmitter enable. fte = 1 activates the fdl transmitter. fte = 0 forces the fdl transmitter into an inactive state. this bit resets to 0. 4frr fdl receiver reset. frr = 1 g enerates an internal pulse that resets the fdl receiver. the fdl receiver fifo and related circuitr y are cleared. the freof, frf, fridl, and overrun interrupts are cleared. this bit resets to 0. 5ftr fdl transmitter reset. ftr = 1 g enerates an internal pulse that resets the fdl trans- mitter. the fdl transmit fifo and related circuitr y are cleared. the ftundabt bit is cleared, and the ftem interrupt is set; the ftdone bit is forced to 0 in the hdlc mode and forced to 1 in the transparent mode. this bit resets to 0. 6frpf fdl receive prm frames. frpf = 1 allows the receive fdl unit to write the entire receive performance report messa g e includin g the frame header and crc data into the receive fdl fifo. this bit resets to 0. 7ftprm transmit prm enable. when this bit is set, the receive framer will write into the transmit fdl fifo its performance report messa g e data. the current second of this data is stored in the receive framers status re g isters. the receive framers prm is transmitted once per second. the prm is followed b y either idles or fla g s transmitted after the prm. when this bit is 0, the transmit fdl expects data from the microprocessor interface. preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 170 lucent technologies inc. lucent technologies inc. fdl parameter/control registers ((a00a0e); (a20a2e); (b00b0e); (b20b2e) (c00c0e); (c20c2e); (d00d0e); (d20d2e)) (continued) table 167. fdl interrupt mask control register (fdl_pr2) (a02; a22; b02; b22; c02; c22; d02; d22) bit symbol description 0ftdie fdl transmit-done interru p t enable. when this interrupt enable bit is set, an interrupt pin transition is g enerated after the last bit of the closin g fla g or abort se q uence is sent. in the transparent mode ( re g ister fdl_pr9 bit 6 = 1 ) , an interrupt pin transition is g enerated when the transmit fifo is completel y empt y . ftdie is cleared upon reset. 1fteie fdl transmitter-em p t y interru p t enable. when this interrupt-enable bit is set, an interrupt pin transition is g enerated when the transmit fifo has reached the pro- g rammed empt y level ( see re g ister fdl_pr3 ) . fteie is cleared upon reset. 2 ftundie fdl transmit underrun interru p t enable. when this interrupt-enable bit is set, an interrupt pin transition is g enerated when the transmit fifo has underrun. ftundie is cleared upon reset and is not used in the transparent mode. 3frfie fdl receiver-full interru p t enable. when this interrupt-enable bit is set, an interrupt pin transition is g enerated when the receive fifo has reached the pro- g rammed full level ( see re g ister fdl_pr6 ) . frfie is cleared upon reset. 4freofie fdl receive end-of-frame interru p t enable. when this interrupt-enable bit is set, an interrupt pin transition is g enerated when an end-of-frame is detected b y the fdl receiver. freofie is cleared upon reset and is not used in the transparent mode. 5frovie fdl receiver overrun interru p t enable. when this interrupt-enable bit is set, an interrupt pin transition is g enerated when the receive fifo overruns. frovie is cleared upon reset. 6 friie fdl receiver idle-interru p t enable. when this interrupt-enable bit is set, an interrupt pin transition is g enerated when the receiver enters the idle state. friir is cleared upon reset and is not used in the transparent mode. 7 ftbcrc fdl transmit bad crc. settin g this bit to 1 forces bad crcs to be sent on all transmit- ted frames ( for test purposes ) until the ftbcrc bit is cleared to 0. lucent technologies inc. 171 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. fdl parameter/control registers ((a00a0e); (a20a2e); (b00b0e); (b20b2e) (c00c0e); (c20c2e); (d00d0e); (d20d2e)) (continued) table 168. fdl transmitter configuration control register (fdl_pr3) (a03; a23; b03; b23; c03; c23; d03; d23) 1. do not set ftabt = 1 and ftfc = 1 at the same time. table 169. fdl transmitter fifo register (fdl_pr4) (a04; a24; b04; b24; c04; c24; d04; d24) table 170. fdl transmitter idle character register (fdl_pr5) (a05; a25; b05; b25; c05; c25; d05; d25) bit symbol description 05 ftil0ftil5 fdl transmitter interru p t level. these bits specif y the minimum number of empt y positions in the transmit fifo which tri gg ers a transmitter-empt y ( ftem ) interrupt. encodin g is in binar y ; bit 0 is the least si g nificant bit. a code of 001010 will g enerate an interrupt when the transmit fifo has ten or more empt y locations. the code 000000 g enerates an interrupt when the transmit fifo is empt y . the number of empt y transmit fifo locations is obtained b y readin g the transmit fdl status re g ister fdl_sr1. 6 1 ftabt fdl transmitter abort. ftabt = 1 forces the transmit fdl unit to abort the frame at the last user data b y te waitin g for transmission. when the transmitter reads the b y te ta gg ed with ftabt, the abort se q uence ( 01111111 ) is transmitted in its place. a full b y te is g uar- anteed to be transmitted. once set for a specific data b y te, the internal ftabt status cannot be cleared b y writin g to this bit. clearin g this bit has no effect on a previousl y writ- ten ftabt. the last value written to ftabt is available for readin g . 7 1 ftfc fdl transmitter frame com p lete. ftfc = 1 forces the transmit fdl unit to terminate the frame normall y after the last user data b y te is written to the transmit fifo. the crc se q uence and a closin g fla g are appended. ftfc should be set to 1 within 1 ms of writ- in g the last b y te of the frame in the transmit fifo. when the transmit fifo is empt y , writ- in g two data b y tes to the fifo before settin g ftcf provides a minimum of 1 ms to write ftfc = 1. once set for a specific data b y te, the internal ftfc status bit cannot be cleared b y writin g to this bit. clearin g this bit has no effect on a previousl y written ftfc. the last value written to ftfc is available for readin g . bit symbol description 07 ftd0ftd7 fdl transmit data. the user data to be transmitted via the fdl block are loaded throu g h this re g ister. bit symbol description 07 ftic0ftic7 fdl transmitter idle character. this character is used onl y in transparent mode ( re g is- ter fdl_pr9 bit 6 = 1 ) . when the pattern match bit ( re g ister fdl_pr9 bit 5 ) is set to 1, the fdl transmit unit sends this character whenever the transmit fifo is empt y . the default is to send the ones idle character, but an y character can be pro g rammed b y the user. preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 172 lucent technologies inc. lucent technologies inc. fdl parameter/control registers ((a00a0e); (a20a2e); (b00b0e); (b20b2e) (c00c0e); (c20c2e); (d00d0e); (d20d2e)) (continued) table 171. fdl receiver interrupt level control register (fdl_pr6) (a06; a26; b06; b26; c06; c26; d06; d26) table 172. fdl register fdl_pr7 table 173. fdl receiver match character register (fdl_pr8) (a08; a28; b08; b28; c08; c28; d08; d28) bit symbol description 05 fril0fril5 fdl receive interru p t level. bit 0bit 5 define receiver fifo full threshold value that will g enerate the correspondin g frf interrupt. fril = 000000 forces the receive fdl fifo to g enerate an interrupt when the receive fifo is completel y full. fril = 001111 will force the receive fdl fifo to g enerate an interrupt when the receive fifo contains 15 or more b y tes. 6 reserved. write to 0. 7 fransie fdl receiver ansi bit codes interru p t enable. if this bit is set to 1, an interrupt pin condition is g enerated whenever a valid ansi code is received. bit symbol description 07 reserved. bit symbol description 07 frmc0 frmc7 receiver fdl match character. this character is used onl y in transparent mode ( re g is- ter fdl_pr9 bit 6 = 1 ) . when the pattern match bit ( re g ister fdl_pr9 bit 5 ) is set to 1, the receive fdl unit searches the incomin g bit stream for the receiver match character. data is loaded into the receive fifo onl y after this character has been identified. the b y te identified as matchin g the receiver match character is the first b y te loaded into the receive fifo. the default is to search for a fla g , but an y character can be pro g rammed b y the user. the search for the receiver match character can be in a slidin g window fash- ion ( re g ister fdl_pr9 bit 4 = 0 ) or onl y on b y te boundaries ( re g ister fdl_pr9 bit 4 = 1 ) . lucent technologies inc. 173 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. fdl parameter/control registers ((a00a0e); (a20a2e); (b00b0e); (b20b2e) (c00c0e); (c20c2e); (d00d0e); (d20d2e)) (continued) table 174. fdl transparent control register (fdl_pr9) (a09; a29; b09; b29; c09; c29; d09; d29) * the octet boundary is relative the first receive clock edge after the receiver has been enabled (enr, fdl_pr1 bit 2 = 1). table 175. fdl transmit ansi esf bit codes (fdl_pr10) (a0a; a2a; b0a; b2a; c0a; c2a; d0a; d2a) bit symbol description 02 foctof0 foctof2 fdl octet offset ( read onl y) . these bits record the offset relative to the octet bound- ar y when the receive character was matched. the foctof bits are valid when re g ister fdl_pr9 bit 3 ( fmstat ) is set to 1. a value of 111 ( binar y) indicates b y te ali g nment. 3fmstat match status ( read onl y) . when this bit is set to 1 b y the receive fdl unit, the receiver match character has been reco g nized. the octet offset status bits ( fdl_pr9 bit [ 2:0 ]) indicates the offset relative to the octet boundar y * at which the receive character was matched. if no match is bein g performed ( re g ister fdl_pr9 bit 5 = 0 ) , the fmstat bit is set to 1 automaticall y when the first b y te is received, and the octet offset status bits ( re g - ister fdl_pr9 bit 0bit 2 ) are set to 111 ( binar y) . 4faloct frame-s y nc ali g n. when this bit is set to 1, the receive fdl unit searches for the receive match character ( fdl-pr8 ) onl y on an octet boundar y . when this bit is 0, the receive fdl unit searches for the receive match character in a slidin g window fashion. 5fmatch pattern match. fmatch affects both the transmitter and receiver. when this bit is set to 1, the fdl does not load data into the receive fifo until the receive match character pro g rammed in re g ister fdl_pr8 has been detected. the search for the receive match character is in a slidin g window fashion if re g ister fdl_pr9 bit 4 is 0, or onl y on octet boundaries if re g ister fdl_pr9 bit 4 is set to 1. when this bit is 0, the receive fdl unit loads the matched b y te and all subse q uent data directl y into the receive fifo. on the transmit side, when this bit is set to 1 the transmitter sends the transmit idle character pro g rammed into re g ister fdl_pr5 when the transmit fifo has no user data. the default idle is to transmit the hdlc ones idle character ( ff hexadecimal ) ; however, an y value can be used b y pro g rammin g the transmit idle character re g ister fdl_pr5. if this bit is 0, the transmitter sends ones idle characters when the transmit fifo is empt y . 6ftm fdl trans p arent mode. when this bit is set to 1, the fdl unit performs no hdlc pro- cessin g on incomin g or out g oin g data. 7 reserved. write to 0. bit symbol description 05 ftansi0 ftansi5 fdl esf bit-oriented messa g e data. the transmit esf fdl bit messa g es are in the form 111111110x 0 x 1 x 2 x 3 x 4 x 5 0, where the order of transmission is from left to ri g ht. 6 reserved. write to 0. 7ftansi transmit ansi bit codes. when this bit is set to 1, the fdl unit will continuousl y trans- mit the ansi code defined usin g re g ister fdl_pr10 bit 0bit 5 as the esf bit code messa g es. this bit must sta y hi g h lon g enou g h to ensure the ansi code is sent at least 10 times. preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 174 lucent technologies inc. lucent technologies inc. fdl parameter/control registers ((a00a0e); (a20a2e); (b00b0e); (b20b2e) (c00c0e); (c20c2e); (d00d0e); (d20d2e)) (continued) table 176. fdl interrupt status register (clear on read) (fdl_sr0) (a0b; a2b; b0b; b2b; c0b; c2b; d0b; d2b) * if an fdl receive fifo overrun occurs, as indicated by register fdl_sr0 bit 5 (froverun) = 1, the fdl must be reset to restore proper operation of the fifo. following an fdl receive fifo overrun, data extracted prior to the required reset may be corrupted. bit symbol description 0ftdone transmit done. this status bit is set to 1 when transmission of the current fdl frame has been completed, either after the last bit of the closin g fla g or after the last bit of an abort se q uence. in the transparent mode ( fdl_pr9 bit 6 = 1 ) , this status bit is set when the transmit fifo is completel y empt y . a hardware interrupt is g enerated onl y if the cor- respondin g interrupt-enable bit ( fdl_pr2 bit 0 ) is set. this status bit is cleared to 0 b y a read of this re g ister. 1ftem transmitter em p t y . if this bit is set to 1, the fdl transmit fifo is at or below the pro- g rammed depth. a hardware interrupt is g enerated onl y if the correspondin g interrupt- enable bit ( fdl_pr2 bit 1 ) is set. if dint ( fdl_pr0 bit 0 ) is 0, this status bit is cleared b y a read of this re g ister. if fdint ( fdl_pr0 bit 0 ) is set to 1, this bit actuall y represents the d y namic transmit empt y condition, and is cleared to 0 onl y when the transmit fifo is loaded above the pro g rammed empt y level. 2 ftundabt fdl transmit underrun abort. a 1 indicates that an abort was transmitted because of a transmit fifo underrun. a hardware interrupt is g enerated onl y if the correspondin g interrupt-enable bit ( fdl_pr2 bit 2 ) is set. this status bit is cleared to 0 b y a read of this re g ister. this bit must be cleared to 0 before further transmission of data is allowed. this interrupt is not g enerated in the transparent mode. 3frf fdl receiver full. this bit is set to 1 when the receive fifo is at or above the pro- g rammed full level ( fdl_pr6 ) . a hardware interrupt is g enerated if the correspondin g interrupt-enable bit ( fdl_pr2 bit 3 ) is set. if fdint ( fdl_pr0 bit 0 ) is 0, this status bit is cleared to 0 b y a read of this re g ister. if fdint ( fdl_pr0 bit 0 ) is set to 1, then this bit is cleared onl y when the receive fifo is read ( or emptied ) below the pro g rammed full level*. 4freof fdl receive end of frame. this bit is set to 1 when the receiver has finished receivin g a frame. it becomes 1 upon reception of the last bit of the closin g fla g of a frame or the last bit of an abort se q uence. a hardware interrupt is g enerated onl y if the correspondin g interrupt-enable bit ( fdl_pr2 bit 4 ) is set. this status bit is cleared to 0 b y a read of this re g ister. this interrupt is not g enerated in the transparent mode. 5froverun fdl receiver overrun. this bit is set to 1 when the receive fifo has overrun its capacit y . a hardware interrupt is g enerated onl y if the correspondin g interrupt-enable bit ( fdl_pr2 bit 5 ) is set. this status bit is cleared to 0 b y a read of this re g ister*. 6 fridl fdl receiver idle. this bit is set to 1 when the fdl receiver is idle ( i.e., 15 or more consecutive ones have been received ) . a hardware interrupt is g enerated onl y if the cor- respondin g interrupt-enable bit ( fdl_pr2 bit 6 ) is set. this status bit is cleared to 0 b y a read of this re g ister. this interrupt is not g enerated in the transparent mode. 7 fransi fdl receive ansi bit codes. this bit is set to 1 when the fdl receiver reco g nizes a valid t1.403 esf fdl bit code. the receive ansi bit code is stored in re g ister fdl_sr3. an interrupt is g enerated onl y if the correspondin g interrupt enable of re g ister fdl_pr6 bit 7 = 1. this status bit is cleared to 0 b y a read this re g ister. lucent technologies inc. 175 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. fdl parameter/control registers ((a00a0e); (a20a2e); (b00b0e); (b20b2e) (c00c0e); (c20c2e); (d00d0e); (d20d2e)) (continued) table 177. fdl transmitter status register (fdl_sr1) (a0c; a2c; b0c; b2c; c0c; c2c; d0c; d2c) * the count of fdl_sr1 bits 06 includes sf byte. table 178. fdl receiver status register (fdl_sr2) (a0d; a2d; b0d; b2d; c0d; c2d; d0d; d2d) * immediately following an fdl reset, the value in bit 0bit 6 of this status register is 0. after the initial read of the fdl r eceive fifo, the value in bit 0bit 6 of this status register is the number of bytes, including sf byte, that may be read from the fifo. received fdl ansi bit codes status register (fdl_sr3) the 6-bit code extracted from the ansi code 111111110x 0 x 1 x 2 x 3 x 4 x 5 0 is stored in this register. table 179. receive ansi fdl status register (fdl_sr3) (a0e; a2e; b0e; b2e; c0e; c2e; d0e; d2e) receive fdl fifo register (fdl_sr4) this fifo stores the received fdl data. only valid fifo bytes indicated in register fdl_sr2 may be read. read- ing nonvalid fifo locations or reading the fifo when it is empty will corrupt the fifo pointer and will require an fdl reset to restore proper fdl operation. table 180. fdl receiver fifo register (fdl_sr4) (a07; a27; b07; b27; c07; c27; d07; d27) bit symbol description 06 ftqs0 ftqs6 fdl transmit queue status. bit 0bit 6 indicate how man y b y tes can be added to the transmit fifo*. the bits are encoded in binar y where bit 0 is the least si g nificant bit. 7fted fdl transmitter em p t y d y namic. fted = 1 indicates that the number of empt y loca- tions available in the transmit fifo is g reater than or e q ual to the value pro g rammed in the ftil bits ( fdl_pr3 ) . bit symbol description 06 frqs0 frqs6 fdl receive queue status. bit 0bit 6 indicate how man y b y tes are in the receive fifo, includin g the first status of frame ( sf ) b y te . the bits are encoded in binar y where bit 0 is the least si g nificant bit*. 7feof fdl end of frame. when feof = 1, the receive q ueue status indicates the number of b y tes up to and includin g the first sf b y te. b7 b6 b5 b4 b3 b2 b1 b0 0 0 x5 x4 x3 x2 x1 x0 bit symbol description 07 frd0frd7 fdl receive data. the user data received via the fdl block are read throu g h this re g - ister. preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 176 lucent technologies inc. lucent technologies inc. register maps global registers table 181. global register set re g ister clear on read (cor) read (r) write (w) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 re g ister address (hex) greg0 cor frmr8_int (0) frmr7_int (0) frmr6_int (0) frmr5_int (0) frmr4_int (0) frmr3_int (0) frmr2_int (0) frmr1_int (0) 000 greg1 r/w frmr8ie (0) frmr7ie (0) frmr6ie (0) frmr5ie (0) frmr4ie (0) frmr3ie (0) frmr2ie (0) frmr1ie (0) 001 greg2 r/w fdl8_int (0) fdl7_int (0) fdl6_int (0) fdl5_int (0) fdl4_int (0) fdl3_int (0) fdl2_int (0) fdl1_int (0) 002 greg3 r/w fdl8ie (0) fdl7ie (0) fdl6ie (0) fdl5ie (0) fdl4e (0) fdl3ie (0) fdl2ie (0) fdl1ie (0) 003 greg4 r/w reserved (0) ipc (0) reserved (0) itsc (0) reserved (0) secctrl0 (0) secctrl1 (0) secctrl2 (0) 004 greg5r11111000005 greg6r00000011006 greg7r00000001007 greg8 r/w reserved (0) divmux0 (0) divmux1 (0) divmux2 (0) reserved (0) lomux0 (0) lomux1 (0) lomux2 (0) 008 greg9 r/w eipllck8 (0) eipllck7 (0) eipllck6 (0) eipllck5 (0) eipllck4 (0) eipllck3 (0) eipllck2 (0) eipllck1 (0) 009 lucent technologies inc. 177 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. register maps (continued) framer parameter/control registers (read-write) the address of the registers is shown with the most significant digit, designated by y, which is used to identify each framer (for framer 1framer 8, y = 29, respectively). table 182. framer unit status register map framer status clear on read (cor) read (r) write (w) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register address (hex) framer 18 frm_sr0 cor s96sr 0 rssfe tssfe ese fae rac fac y00 frm_sr1 cor ais auxp rts16ais lbfa lfalr ltsfa lts0mfa lsfa lts16mfa lfa y01 frm_sr2 cor rsa6=f rsa6=e rsa6=c rsa6=a rsa6=8 crebit rjya rts16mfa rfa y02 frm_sr3 cor slipu slipo lcrcatmx rebit ece crce fbe lfv y03 frm_sr4 cor fdl-llboff tsasr fdl-llbon rsasr fdl-plboff fdl-plbon llbon cma llboff bfa ssfa nfa y04 frm_sr5 cor etreuas etreses etrebes etrees etuas etses etbes etes y05 frm_sr6 cor ntreuas ntreses ntrebes ntrees ntuas ntses ntbes ntes y06 frm_sr7 cor rquasi rpseudo ptrnber detect nrouas nt1ouas erouas ouas y07 frm_sr8 cor bpv15 bpv14 bpv13 bpv12 bpv11 bpv10 bpv9 bpv8 y08 frm_sr9 cor bpv7 bpv6 bpv5 bpv4 bpv3 bpv2 bpv1 bpv0 y09 frm_sr10 cor fe15 fe14 fe13 fe12 fe11 fe10 fe9 fe8 y0a frm_sr11 cor fe7fe6fe5fe4fe3fe2fe1fe0 y0b frm_sr12 cor cec15 cec14 cec13 cec12 cec11 cec10 cec9 cec8 y0c frm_sr13 cor cec7 cec6 cec5 cec4 cec3 cec2 cec1 cec0 y0d frm_sr14 cor rec15 rec14 rec13 rec12 rec11 rec10 rec9 rec8 y0e frm_sr15 cor rec7 rec6 rec5 rec4 rec3 rec2 rec1 rec0 y0f frm_sr16 cor cnt15 cnt14 cnt13 cnt12 cnt11 cnt10 cnt9 cnt8 y10 frm_sr17 cor cnt7 cnt6 cnt5 cnt4 cnt3 cnt2 cnt1 cnt0 y11 frm_sr18 cor ent15 ent14 ent13 ent12 ent11 ent10 ent9 ent8 y12 frm_sr19 cor ent7 ent6 ent5 ent4 ent3 ent2 ent1 ent0 y13 frm_sr20 cor etes15 etes14 etes13 etes12 etes11 etes10 etes9 etes8 y14 frm_sr21 cor etes7 etes6 etes5 etes4 etes3 etes2 etes1 etes0 y15 frm_sr22 cor etbes15 etbes14 etbes13 etbes12 etbes11 etbes10 etbes9 etbes8 y16 frm_sr23 cor etbes7 etbes6 etbes5 etbes4 etbes3 etbes2 etbes1 etbes0 y17 frm_sr24 cor etses15 etses14 etses13 etses12 etses11 etses10 etses9 etses8 y18 frm_sr25 cor etses7 etses6 etses5 etses4 etses3 etses2 etses1 etses0 y19 frm_sr26 cor etus15 etus14 etus13 etus12 etus11 etus10 etus9 etus8 y1a frm_sr27 cor etus7 etus6 etus5 etus4 etus3 etus2 etus1 etus0 y1b frm_sr28 cor etrees15 etrees14 etrees13 etrees12 etrees11 etrees10 etrees9 etrees8 y1c frm_sr29 cor etrees7 etrees6 etrees5 etrees4 etrees3 etrees2 etrees1 etrees0 y1d frm_sr30 cor etrebes15 etrebes14 etrebes13 etrebes12 etrebes11 etrebes10 etrebes9 etrebes8 y1e frm_sr31 cor etrebes7 etrebes6 etrebes5 etrebes4 etrebes3 etrebes2 etrebes1 etrebes0 y1f frm_sr32 cor etreses15 etreses14 etreses13 etreses12 etreses11 etreses10 etreses9 etreses8 y20 frm_sr33 cor etreses7 etreses6 etreses5 etreses4 etreses3 etreses2 etreses1 etreses0 y21 frm_sr34 cor etreus15 etreus14 etreus13 etreus12 etreus11 etreus10 etreus9 etreus8 y22 frm_sr35 cor etreus7 etreus6 etreus5 etreus4 etreus3 etreus2 etreus1 etreus0 y23 preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 178 lucent technologies inc. lucent technologies inc. register maps (continued) table 182. framer unit status register map (continued) * unbracketed contents are valid for ds1 modes. bracketed contents, [], are valid for cept mode. framer status clear on read (cor) read (r) write (w) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register address (hex) framer 18 frm_sr36 cor ntes15 ntes14 ntes13 ntes12 ntes11 ntes10 ntes9 ntes8 y24 frm_sr37 cor ntes7 ntes6 ntes5 ntes4 ntes3 ntes2 ntes1 ntes0 y25 frm_sr38 cor ntbes15 ntbes14 ntbes13 ntbes12 ntbes11 ntbes10 ntbes9 ntbes8 y26 frm_sr39 cor ntbes7 ntbes6 ntbes5 ntbes4 ntbes3 ntbes2 ntbes1 ntbes0 y27 frm_sr40 cor ntses15 ntses14 ntses13 ntses12 ntses11 ntses10 ntses9 ntses8 y28 frm_sr41 cor ntses7 ntses6 ntses5 ntses4 ntses3 ntses2 ntses1 ntses0 y29 frm_sr42 cor ntus15 ntus14 ntus13 ntus12 ntus11 ntus10 ntus9 ntus8 y2a frm_sr43 cor ntus7 ntus6 ntus5 ntus4 ntus3 ntus2 ntus1 ntus0 y2b frm_sr44 cor ntrees15 ntrees14 ntrees13 ntrees12 ntrees11 ntrees10 ntrees9 ntrees8 y2c frm_sr45 cor ntrees7 ntrees6 ntrees5 ntrees4 ntrees3 ntrees2 ntrees1 ntrees0 y2d frm_sr46 cor ntrebes15 ntrebes14 ntrebes13 ntrebes12 ntrebes11 ntrebes10 ntrebes9 ntrebes8 y2e frm_sr47 cor ntrebes7 ntrebes6 ntrebes5 ntrebes4 ntrebes3 ntrebes2 ntrebes1 ntrebes0 y2f frm_sr48 cor ntreses15 ntreses14 ntreses13 ntreses12 ntreses11 ntreses10 ntreses9 ntreses8 y30 frm_sr49 cor ntreses7 ntreses6 ntreses5 ntreses4 ntreses3 ntreses2 ntreses1 ntreses0 y31 frm_sr50 cor ntreus15 ntreus14 ntreus13 ntreus12 ntreus11 ntreus10 ntreus9 ntreus8 y32 frm_sr51 cor ntreus7 ntreus6 ntreus5 ntreus4 ntreus3 ntreus2 ntreus1 ntreus0 y33 frm_sr52 cor nfb1 [fi5e] fbi [fi3e] a bit sa4 sa5 sa6 sa7 sa8 y34 frm_sr53 cor 0 0 0 0 0 rx2 rx1 rx0 y35 frm_sr54 * cor 0 [sa4-1] 0 [sa4-3] r-0 [sa4-5] r-0 [sa4-7] r-0 [sa4-9] r-1 [sa4-11] r-1 [sa4-13] r-1 [sa4-15] y36 frm_sr55 * cor 0 [sa4-17] 0 [sa4-19] r-0 [sa4-21] r-0 [sa4-23] r-0 [sa4-25] r-1 [sa4-27] r-1 [sa4-29] r-1 [sa4-31] y37 frm_sr56 * cor rc 1 [sa5-1] rc 2 [sa5-3] rc 3 [sa5-5] rc 4 [sa5-7] rc 5 [sa5-9] rc 6 [sa5-11] rc 7 [sa5-13] rc 8 [sa5-15] y38 frm_sr57 * cor rc 9 [sa5-17] rc 10 [sa5-19] rc 11 [sa5-21] rspb 1 = 0 [sa5-23] rspb 2 = 1 [sa5-25] rspb 3 = 0 [sa5-27] rm 1 [sa5-29] rm 2 [sa5-31] y39 frm_sr58 * cor rm 3 [sa6-1] ra 1 [sa6-3] ra 2 [sa6-5] rs 1 [sa6-7] rs 2 [sa6-9] rs 3 [sa6-11] rs 4 [sa613] rspb 4 = 1 [sa6-15] y3a frm_sr59 * cor 0 [sa6-17] 0 [sa6-19] 0 [sa6-21] 0 [sa6-23] 0 [sa6-25] 0 [sa6-27] 0 [sa6-29] 0 [sa6-31] y3b frm_sr60 * cor 0 [sa7-1] 0 [sa7-3] 0 [sa7-5] 0 [sa7-7] 0 [sa7-9] 0 [sa7-11] 0 [sa7-13] 0 [sa7-15] y3c frm_sr61 * cor 0 [sa7-17] 0 [sa7-19] 0 [sa7-21] 0 [sa7-23] 0 [sa7-25] 0 [sa7-27] 0 [sa7-29] 0 [sa7-31] y3d frm_sr62 * cor g3 [sa8-1] lv [sa8-3] g4 [sa8-5] u1 [sa8-7] u2 [sa8-9] g5 [sa8-11] sl [sa8-13] g6 [sa8-15] y3e frm_sr63 * cor fe [sa8-17] se [sa8-19] lb [sa8-21] g1 [sa8-23] r [sa8-25] g2 [sa8-27] nm [sa8-29] nl [sa8-31] y3f lucent technologies inc. 179 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. register maps (continued) receive framer signaling registers (read-only) the address of the registers is shown with the most significant digit, designated by y, which is used to identify each framer (for framer 1framer 8, y = 29, respectively). table 183. receive signaling registers map 1. in the ds1 robbed-bit signaling modes, these bits are copied from the corresponding transmit signaling registers. in the cep t signaling mo des, these bits are in the 0-state and should be ignored. 2. in the ds1 signaling modes, these registers contain unknown data. 3. in ds1 4-state and 2-state signaling, these bits contain unknown data. 4. in ds1 2-state signaling, these bits contain unknown data. 5. in the cept signaling modes, the a-, b-, c-, d-, and p-bit information of these registers contains unknown data. 6. signifies unknown data. receive signaling clear on read (cor) read (r) write (w) bit 7 bit 6 1 bit 5 1 bit 4 2 bit 3 3 bit 2 3 bit 1 4 bit 0 register address (hex) framer 18 frm_rsr0 5 r p g_0f_0e_0d_0c_0b_0a_0 y40 frm_rsr1 r p g_1 f_1 e_1 d_1 c_1 b_1 a_1 y41 frm_rsr2 r p g_2f_2e_2d_2c_2b_2a_2 y42 frm_rsr3 r p g_3 f_3 e_3 d_3 c_3 b_3 a_3 y43 frm_rsr4 r p g_4f_4e_4d_4c_4b_4a_4 y44 frm_rsr5 r p g_5 f_5 e_5 d_5 c_5 b_5 a_5 y45 frm_rsr6 r p g_6f_6e_6d_6c_6b_6a_6 y46 frm_rsr7 r p g_7 f_7 e_7 d_7 c_7 b_7 a_7 y47 frm_rsr8 r p g_8f_8e_8d_8c_8b_8a_8 y48 frm_rsr9 r p g_9 f_8 e_8 d_8 c_8 b_8 a_8 y49 frm_rsr10 r p g_10 f_10 e_10 d_10 c_10 b_10 a_10 y4a frm_rsr11 r p g_11 f_11 e_11 d_11 c_11 b_11 a_11 y4b frm_rsr12 r p g_12 f_12 e_12 d_12 c_12 b_12 a_12 y4c frm_rsr13 r p g_13 f_13 e_13 d_13 c_13 b_13 a_13 y4d frm_rsr14 r p g_14 f_14 e_14 d_14 c_14 b_14 a_14 y4e frm_rsr15 r p g_15 f_15 e_15 d_15 c_15 b_15 a_15 y4f frm_rsr16 5 r p g_16 f_16 e_16 d_16 c_16 b_16 a_16 y50 frm_rsr17 r p g_17 f_17 e_17 d_17 c_17 b_17 a_17 y51 frm_rsr18 r p g_18 f_18 e_18 d_18 c_18 b_18 a_18 y52 frm_rsr19 r p g_19 f_19 e_19 d_19 c_19 b_19 a_19 y53 frm_rsr20 r p g_20 f_20 e_20 d_20 c_20 b_20 a_20 y54 frm_rsr21 r p g_21 f_21 e_21 d_21 c_21 b_21 a_21 y55 frm_rsr22 r p g_22 f_22 e_22 d_22 c_22 b_22 a_22 y56 frm_rsr23 r p g_23 f_23 e_23 d_23 c_23 b_23 a_23 y57 frm_rsr24 2 rpx 7 x e_24 d_24 c_24 b_24 a_24 y58 frm_rsr25 2 r p x x e_25 d_25 c_25 b_25 a_25 y59 frm_rsr26 2 r p x x e_26 d_26 c_26 b_26 a_26 y5a frm_rsr27 2 r p x x e_27 d_27 c_27 b_27 a_27 y5b frm_rsr28 2 r p x x e_28 d_28 c_28 b_28 a_28 y5c frm_rsr29 2 r p x x e_29 d_29 c_29 b_29 a_29 y5d frm_rsr30 2 r p x x e_30 d_30 c_30 b_30 a_30 y5e frm_rsr31 2 r p x x e_31 d_31 c_31 b_31 a_31 y5f preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 180 lucent technologies inc. lucent technologies inc. register maps (continued) framer unit parameter register map the address of the registers is shown with the most significant digit, designated by y, which is used to identify each framer (for framer 1framer 8, y = 29, respectively). table 184. framer unit parameter register map * definition in cept mode. framer control clear on read (cor) read (r) write (w) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 re g ister address (hex) framer 18 frm_pr0 r/w slcie (0) reserved (0) rsrie (0) tsrie (0) sr567ie (0) sr34ie (0) sr2ie (0) sr1ie (0) y60 frm_pr1 r/w sr1b7ie (0) sr1b6ie (0) sr1b5ie (0) sr1b4ie (0) sr1b3ie (0) sr1b2ie (0) sr1b1ie (0) sr1b0ie (0) y61 frm_pr2 r/w sr2b7ie (0) sr2b6ie (0) sr2b5ie (0) sr2b4ie (0) sr2b3ie (0) sr2b2ie (0) sr2b1ie (0) sr2b0ie (0) y62 frm_pr3 r/w sr3b7ie (0) sr3b6ie (0) sr3b5ie (0) sr3b4ie (0) sr3b3ie (0) sr3b2ie (0) sr3b1ie (0) sr3b0ie (0) y63 frm_pr4 r/w sr4b7ie (0) sr4b6ie (0) sr4b5ie (0) sr4b4ie (0) sr4b3ie (0) sr4b2ie (0) sr4b1ie (0) sr4b0ie (0) y64 frm_pr5 r/w sr5b7ie (0) sr5b6ie (0) sr5b5ie (0) sr5b4ie (0) sr5b3ie (0) sr5b2ie (0) sr5b1ie (0) sr5b0ie (0) y65 frm_pr6 r/w sr6b7ie (0) sr6b6ie (0) sr6b5ie (0) sr6b4ie (0) sr6b3ie (0) sr6b2ie (0) sr6b1ie (0) sr6b0ie (0) y66 frm_pr7 r/w sr7b7ie (0) sr7b6ie (0) sr7b5ie (0) sr7b4ie (0) sr7b3ie (0) sr7b2ie (0) sr7b1ie (0) sr7b0ie (0) y67 frm_pr8 r/w lc2 (1) lc1 (1) lc0 (0) fmode4 (0) fmode3 (0) fmode2 (0) fmode1 (0) fmode0 (0) y68 frm_pr9 r/w crco7 (0) crco6 (0) crco5 (0) crco4 (0) crco3 (0) crco2 (0) crco1 (0) crco0 (0) y69 frm_pr10 r/w esm1 (0) esm0 (0) rabf (0) reserved (0) cnuclben (0) feren [nffe] * (0) aism (0) ssa6m (0) y6a frm_pr11 r/w est7 (0) est6 (0) est5 (0) est4 (0) est3 (0) est2 (0) est1 (0) est0 (0) y6b frm_pr12 r/w sest15 (0) sest14 (0) sest13 (0) sest12 (0) sest11 (0) sest10 (0) sest9 (0) sest8 (0) y6c frm_pr13 r/w sest7 (0) sest6 (0) sest5 (0) sest4 (0) sest3 (0) sest2 (0) sest1 (0) sest0 (0) y6d frm_pr14 r/w 0000etslip (0) etais (0) etlmfa (0) etlfa (0) y6e frm_pr15 r/w etresa6-f (0) etresa6-e (0) etresa6-8 (0) etrerfa (0) etreslip (0) etreais (0) etrelmfa (0) etrelfa (0) y6f frm_pr16 r/w ntsa6-c (0) 0 ntsa6-8 (0) 0ntslip (0) ntais (0) ntlmfa (0) ntlfa (0) y70 frm_pr17 r/w 0 0 0 ntrerfa (0) ntreslip (0) ntreais (0) ntrelmfa (0) ntrelfa (0) y71 frm_pr18 r/w 0000ntresa6-c (0) ntresa6-f (0) ntresa6-e (0) ntresa6-8 (0) y72 frm_pr19 r/w afdplbe (0) afdllbe (0) reserved (0) allbe (0) tsais (0) reserved (0) asaistmx (0) asais (0) y73 frm_pr20 r/w ticrc (0) tlic (0) tllboff (0) tllbon (0) tqrs (0) tprs (0) tufauxp (0) tufais (0) y74 lucent technologies inc. 181 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. register maps (continued) table 184. framer unit parameter register map (continued) framer control clear on read (cor) read (r) write (w) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register address (hex) framer 18 frm_pr21 r/w tc/r=1 (0) tfdlc (0) tfdlsais (0) tfdllais (0) reserved (0) reserved (0) reserved (0) reserved (0) y75 frm_pr22 r/w tlic7 (0) tlic6 (1) tlic5 (1) tlic4 (1) tlic3 (1) tlic2 (1) tlic1 (1) tlic0 (1) y76 frm_pr23 r/w sstsc7 (0) sstsc6 (1) sstsc5 (1) sstsc4 (1) sstsc3 (1) sstsc2 (1) sstsc1 (1) sstsc0 (1) y77 frm_pr24 r/w lbc2 (0) lbc1 (0) lbc0 (0) tslba4 (0) tslba3 (0) tslba2 (0) tslba1 (0) tslba0 (0) y78 frm_pr25 r/w reserved (0) slbc1 (0) slbc0 (0) stslba4 (0) stslba3 (0) stslba2 (0) stslba1 (0) stslba0 (0) y79 frm_pr26 r/w reserved (0) reserved (0) sysfsm (0) tfm2 (0) tfm1 (0) frfrm (0) swrestart (0) swreset (0) y7a frm_pr27 r/w trfa (0) tjrfa (0) aarsa6_c (0) aarsa6_8 (0) at m x (0) aab0lmfa (0) aab16lmfa (0) arlfa (0) y7b frm_pr28 r/w 0 0 atertx (0) at e lt s 0 m fa (0) atecrce (0) tsinf (0) tsif (0) sis, t1e (0) y7c frm_pr29 r/w sas7 (0) sas6 (0) sas5 (0) tsa8 (0) tsa7 (0) tsa6 (0) tsa5 (0) tsa4 (0) y7d frm_pr30 r/w tdnf (0) reserved (0) reserved (0) tesa8 (0) tesa7 (0) tesa6 (0) tesa5 (0) tesa4 (0) y7e frm_pr31 r/w 0 sa4-1 0 sa4-3 x-0 sa4-5 x-0 sa4-7 x-0 sa4-9 x-1 sa4-11 x-1 sa4-13 x-1 sa4-15 y7f frm_pr32 r/w 0 sa4-17 0 sa4-19 x-0 sa4-21 x-0 sa4-23 x-0 sa4-25 x-1 sa4-27 x-1 sa4-29 x-1 sa4-31 y80 frm_pr33 r/w xc1 sa5-1 xc2 sa5-3 xc3 sa5-5 xc4 sa5-7 xc5 sa5-9 xc6 sa5-11 xc7 sa5-13 xc8 sa5-15 y81 frm_pr34 r/w xc9 sa5-17 xc10 sa5-19 xc11 sa5-21 xspb1 = 0 sa5-23 xspb2 = 1 sa5-25 xspb3 = 0 sa5-27 xm1 sa5-29 xm2 sa5-31 y82 frm_pr35 r/w xm3 sa6-1 xa1 sa6-3 xa2 sa6-5 xs1 sa6-7 xs2 sa6-9 xs3 sa6-11 xs4 sa613 xspb4 = 1 sa6-15 y83 frm_pr36 r/w sa6-17 sa6-19 sa6-21 sa6-23 sa6-25 sa6-27 sa6-29 sa6-31 y84 frm_pr37 r/w sa7-1 sa7-3 sa7-5 sa7-7 sa7-9 sa7-11 sa7-13 sa7-15 y85 frm_pr38 r/w sa7-17 sa7-19 sa7-21 sa7-23 sa7-25 sa7-27 sa7-29 sa7-31 y86 frm_pr39 r/w sa8-1 sa8-3 sa8-5 sa8-7 sa8-9 sa8-11 sa8-13 sa8-15 y87 frm_pr40 r/w sa8-17 sa8-19 sa8-21 sa8-23 sa8-25 sa8-27 sa8-29 sa8-31 y88 frm_pr41 r/w reserved (0) tlts16ais (0) tlts16rmfa (0) altts16rmfa (0) xs (0) tts16x2 (0) tts16x1 (0) tts16x0 (0) y89 preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 182 lucent technologies inc. lucent technologies inc. register maps (continued) table 184. framer unit parameter register map (continued) framer control clear on read (cor) read (r) write (w) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register address (hex) framer 18 frm_pr42 r/w fex7 (0) fex6 (0) fex5 (0) fex4 (0) fex3 (0) fex2 (0) fex1 (0) fex0 (0) y8a frm_pr43 r/w reserved (0) reserved (0) reserved (0) reserved (0) ssc (0) sts2 [safdl2] (0) sts1 [safdl1] (0) sts0 [safdl0] (1) y8b frm_pr44 r/w tcss (0) astsais (0) tsr-asm (0) mos (0) rsi (0) asm (0) stomp (0) tsig (0) y8c frm_pr45 r/w hwyen (0) reserved (0) reserved (0) chimm (0) cdrs1 (0) cdrs0 (0) cms (0) hflf (0) y8d frm_pr46 r/w rfe (0) roff2 (0) roff1 (0) roff0 (0) tfe (0) toff2 (0) toff1 (0) toff0 (0) y8e frm_pr47 r/w reserved (0) tce (0) tbyoff5 (0) tbyoff4 (0) tbyoff3 (0) tbyoff2 (0) tbyoff1 (0) tbyoff0 (0) y8f frm_pr48 r/w reserved (0) rce (0) rbyoff5 (0) rbyoff4 (0) rbyoff3 (0) rbyoff2 (0) rbyoff1 (0) rbyoff0 (0) y90 frm_pr49 r/w ttse31 (0) ttse30 (0) ttse29 (0) ttse28 (0) ttse27 (0) ttse26 (0) ttse25 (0) ttse24 (0) y91 frm_pr50 r/w ttse23 (0) ttse22 (0) ttse21 (0) ttse20 (0) ttse19 (0) ttse18 (0) ttse17 (0) ttse16 (0) y92 frm_pr51 r/w ttse15 (0) ttse14 (0) ttse13 (0) ttse12 (0) ttse11 (0) ttse10 (0) ttse9 (0) ttse8 (0) y93 frm_pr52 r/w ttse7 (0) ttse6 (0) ttse5 (0) ttse4 (0) ttse3 (0) ttse2 (0) ttse1 (0) ttse0 (0) y94 frm_pr53 r/w rtse31 (0) rtse30 (0) rtse29 (0) rtse28 (0) rtse27 (0) rtse26 (0) rtse25 (0) rtse24 (0) y95 frm_pr54 r/w rtse23 (0) rtse22 (0) rtse21 (0) rtse20 (0) rtse19 (0) rtse18 (0) rtse17 (0) rtse16 (0) y96 frm_pr55 r/w rtse15 (0) rtse14 (0) rtse13 (0) rtse12 (0) rtse11 (0) rtse10 (0) rtse9 (0) rtse8 (0) y97 frm_pr56 r/w rtse7 (0) rtse6 (0) rtse5 (0) rtse4 (0) rtse3 (0) rtse2 (0) rtse1 (0) rtse0 (0) y98 frm_pr57 r/w ths31 (0) ths30 (0) ths29 (0) ths28 (0) ths27 (0) ths26 (0) ths25 (0) ths24 (0) y99 frm_pr58 r/w ths23 (0) ths22 (0) ths21 (0) ths20 (0) ths19 (0) ths18 (0) ths17 (0) ths16 (0) y9a frm_pr59 r/w ths15 (0) ths14 (0) ths13 (0) ths12 (0) ths11 (0) ths10 (0) ths9 (0) ths8 (0) y9b frm_pr60 r/w ths7 (0) ths6 (0) ths5 (0) ths4 (0) ths3 (0) ths2 (0) ths1 (0) ths0 (0) y9c frm_pr61 r/w rhs31 (0) rhs30 (0) rhs29 (0) rhs28 (0) rhs27 (0) rhs26 (0) rhs25 (0) rhs24 (0) y9d frm_pr62 r/w rhs23 (0) rhs22 (0) rhs21 (0) rhs20 (0) rhs19 (0) rhs18 (0) rhs17 (0) rhs16 (0) y9e frm_pr63 r/w rhs15 (0) rhs14 (0) rhs13 (0) rhs12 (0) rhs11 (0) rhs10 (0) rhs9 (0) rhs8 (0) y9f frm_pr64 r/w rhs7 (0) rhs6 (0) rhs5 (0) rhs4 (0) rhs3 (0) rhs2 (0) rhs1 (0) rhs0 (0) ya 0 frm_pr65 r/w reserved (0) reserved (0) reserved (0) reserved (0) reserved (0) reserved (0) tchidts (0) tbyoff6 (0) ya1 frm_pr66 r/w reserved (0) reserved (0) reserved (0) reserved (0) reserved (0) reserved (0) rchidts (0) rbyoff6 (0) ya 2 frm_pr67 reserved reserved reserved reserved reserved reserved reserved reserved ya3 frm_pr68 reserved reserved reserved reserved reserved reserved reserved reserved ya4 frm_pr69 r/w gptrn3 (0) gptrn2 (0) gptrn1 (0) gptrn0 (0) gfrmsel (0) gblksel (0) tpei (0) itd (0) ya5 frm_pr70 r/w dptrn3 (0) dptrn2 (0) dptrn1 (0) dptrn0 (0) duftp (0) dblksel (0) reserved (0) ird (0) ya6 lucent technologies inc. 183 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. register maps (continued) transmit signaling registers (read/write) the address of the registers is shown with the most significant digit, designated by y, which is used to identify each framer (for framer 1framer 8, y = 29, respectively). table 185. transmit signaling registers map 1. in the normal ds1 robbed-bit signaling modes, these bits define the corresponding receive channel signaling mode and are copied into the received signaling registers. in the cept signaling modes, these bits are ignored. 2. these bits contain unknown data. 3. in ds1 4-state and 2-state signaling modes, these bits contain unknown data. 4. in ds1 2-state signaling mode, these bits contain unknown data. 5. in the cept signaling modes, the a-, b-, c-, d-, and p-bit information of these registers contains unknown data. 6. in the ds1 signaling modes, these registers contain unknown data. 7. signifies known data. transmit signaling clear on read ( cor ) read ( r ) write ( w ) bit 7 bit 6 1 bit 5 1 bit 4 2 bit 3 3 bit 2 3 bit 1 4 bit 0 re g ister address ( hex ) framer 18 frm_tsr0 5 r/w p g_0 f_0 d_0 c_0 b_0 a_0 ye0 frm_tsr1 r/w p g_1 f_1 d_1 c_1 b_1 a_1 ye1 frm_tsr2 r/w p g_2 f_2 d_2 c_2 b_2 a_2 ye2 frm_tsr3 r/w p g_3 f_3 d_3 c_3 b_3 a_3 ye3 frm_tsr4 r/w p g_4 f_4 d_4 c_4 b_4 a_4 ye4 frm_tsr5 r/w p g_5 f_5 d_5 c_5 b_5 a_5 ye5 frm_tsr6 r/w p g_6 f_6 d_6 c_6 b_6 a_6 ye6 frm_tsr7 r/w p g_7 f_7 d_7 c_7 b_7 a_7 ye7 frm_tsr8 r/w p g_8 f_8 d_8 c_8 b_8 a_8 ye8 frm_tsr9 r/w p g_9 f_8 d_8 c_8 b_8 a_8 ye9 frm_tsr10 r/w p g_10 f_10 d_10 c_10 b_10 a_10 yea frm_tsr11 r/w p g_11 f_11 d_11 c_11 b_11 a_11 yeb frm_tsr12 r/w p g_12 f_12 d_12 c_12 b_12 a_12 yec frm_tsr13 r/w p g_13 f_13 d_13 c_13 b_13 a_13 yed frm_tsr14 r/w p g_14 f_14 d_14 c_14 b_14 a_14 yee frm_tsr15 r/w p g_15 f_15 d_15 c_15 b_15 a_15 yef frm_tsr16 5 r/w p g_16 f_16 d_16 c_16 b_16 a_16 yf0 frm_tsr17 r/w p g_17 f_17 d_17 c_17 b_17 a_17 yf1 frm_tsr18 r/w p g_18 f_18 d_18 c_18 b_18 a_18 yf2 frm_tsr19 r/w p g_19 f_19 d_19 c_19 b_19 a_19 yf3 frm_tsr20 r/w p g_20 f_20 d_20 c_20 b_20 a_20 yf4 frm_tsr21 r/w p g_21 f_21 d_21 c_21 b_21 a_21 yf5 frm_tsr22 r/w p g_22 f_22 d_22 c_22 b_22 a_22 yf6 frm_tsr23 r/w p g_23 f_23 d_23 c_23 b_23 a_23 yf7 frm_tsr24 6 r/w p x 7 x d_24 c_24 b_24 a_24 yf8 frm_tsr25 6 r/w p x x d_25 c_25 b_25 a_25 yf9 frm_tsr26 6 r/w p x x d_26 c_26 b_26 a_26 yfa frm_tsr27 6 r/w p x x d_27 c_27 b_27 a_27 yfb frm_tsr28 6 r/w p x x d_28 c_28 b_28 a_28 yfc frm_tsr29 6 r/w p x x d_29 c_29 b_29 a_29 yfd frm_tsr30 6 r/w p x x d_30 c_30 b_30 a_30 yfe frm_tsr31 6 r/w p x x d_31 c_31 b_31 a_31 yff preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 184 lucent technologies inc. lucent technologies inc. register maps (continued) facility data link parameter/control and status registers (read-write) table 186. facilit y data link re g ister ma p * for fdl 1 and fdl 2, y = a; for fdl 3 and fdl 4, y = b; for fdl 5 and fdl 6, y = c; for fdl 7 and fdl 8, y = d. transmit signaling clear on read (cor) read (r) write (w) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 re g ister address * (hex) fdl 1 fdl 3 fdl 5 fdl 7 fdl 2 fdl 4 fdl 6 fdl 8 fdl_pr0 r/w fransit3 ( 1 ) fransit2 ( 0 ) fransit1 ( 1 ) fransit0 ( 0 ) reserved ( 0 ) reserved ( 0 ) flags ( 0 ) fdint ( 0 ) y00 y20 fdl_pr1 r/w ftprm ( 0 ) frpf ( 0 ) ftr ( 0 ) frr ( 0 ) fte ( 0 ) fre ( 0 ) fllb ( 0 ) frlb ( 0 ) y01 y21 fdl_pr2 r/w ftbcrc ( 0 ) friie ( 0 ) frovie ( 0 ) freofie ( 0 ) frfie ( 0 ) ftundie ( 0 ) fteie ( 0 ) ftdie ( 0 ) y02 y22 fdl_pr3 r/w ftfc ( 0 ) ftabt ( 0 ) ftil5 ( 0 ) ftil4 ( 0 ) ftil3 ( 0 ) ftil2 ( 0 ) ftil1 ( 0 ) ftil0 ( 0 ) y03 y23 fdl_pr4 r/w ftd7 ( 0 ) ftd6 ( 0 ) ftd5 ( 0 ) ftd4 ( 0 ) ftd3 ( 0 ) ftd2 ( 0 ) ftd1 ( 0 ) ftd0 ( 0 ) y04 y24 fdl_pr5 r/w ftic7 ( 0 ) ftic6 ( 0 ) ftic5 ( 0 ) ftic4 ( 0 ) ftic3 ( 0 ) ftic2 ( 0 ) ftic1 ( 0 ) ftic0 ( 0 ) y05 y25 fdl_pr6 r/w fransie ( 0 ) reserved ( 0 ) fril5 ( 0 ) fril4 ( 0 ) fril3 ( 0 ) fril2 ( 0 ) fril1 ( 0 ) fril0 ( 0 ) y06 y26 fdl_pr7 reserved reserved reserved reserved reserved reserved reserved reserved reserved fdl_pr8 r/w frmc7 ( 0 ) frmc6 ( 0 ) frmc5 ( 0 ) frmc4 ( 0 ) frmc3 ( 0 ) frmc2 ( 0 ) frmc1 ( 0 ) frmc0 ( 0 ) y08 y28 fdl_pr9 r/w reserved ( 0 ) ftm ( 0 ) fmatch ( 0 ) faloct ( 0 ) fmstat ( 0 ) foctof2 ( 0 ) foctof1 ( 0 ) foctof 0 ( 0 ) y09 y29 fdl_pr1 0 r/w ftansi ( 0 ) reserved ( 0 ) ftansi5 ( 0 ) ftansi4 ( 0 ) ftansi3 ( 0 ) ftansi2 ( 0 ) ftansi1 ( 0 ) ftansi0 ( 0 ) y0a y2a fdl_sr0 cor fransi fridl froverun freof frf ftundab t ftem ftdone y0b y2b fdl_sr1 r fted ftqs6 ftqs5 ftqs4 ftqs3 ftqs2 ftqs1 ftqs0 y0c y2c fdl_sr2 r freof frqs6 frqs5 frqs4 frqs3 frqs2 frqs1 frqs0 y0d y2d fdl_sr3 r 0 0 x5 x4 x3 x2 x1 x0 y0e y2e fdl_sr4 r frd7 ( 0 ) frd6 ( 0 ) frd5 ( 0 ) frd4 ( 0 ) frd3 ( 0 ) frd2 ( 0 ) frd1 ( 0 ) frd0 ( 0 ) y07 y27 lucent technologies inc. 185 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are abso- lute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. operating conditions handling precautions although protection circuitry has been designed into this device, proper precautions should be taken to avoid expo- sure to electrostatic discharge (esd) during handling and mounting. lucent employs a human-body model (hbm) and charged-device model (cdm) for esd-susceptibility testing and protection design evaluation. esd voltage thresholds are dependent on the circuit parameters used in the defined model. no industry-wide standard has been adopted for the cdm. however, a standard hbm (resistance = 1500 w, capacitance = 100 pf) is widely used and, therefore, can be used for comparison purposes. the hbm esd threshold presented here was obtained by using these circuit parameters. table 187. esd threshold voltage parameter symbol min max unit v dd suppl y volta g e ran g e v dd C0.5 3.6 v power dissipation (total) p d 0.65 1.0 w maximum volta g e ( di g ital pins ) 5.5*v minimum volta g e ( di g ital pins ) with respect to grnd C0.5 v storage temperature range t stg C65 125 c ambient operating temperature range t a C40 85 c * this maximum rating only applies when the device is powered up with v dd . parameter symbol min typ max unit power suppl y v dd 3.14 3.3 3.47 v hi g h-level input volta g ev ih v dd C 1.0 5.25 v low-level input volta g ev il 01.0v ambient temperature t a C40 85 c device voltage TFRA08C13 >1000 v preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 186 lucent technologies inc. lucent technologies inc. electrical characteristics logic interface characteristics table 188. logic interface characteristics (t a = C40 c to +85 c, v dd = 3.3 v 5%, v ss = 0) * sinking. ? sourcing. notes: all buffers use cmos levels. all inputs are driven between 2.4 v and 0.4 v. an internal pull-up is provided on the 3-state , reset , ds1/cept , mpmode, cs , mpck, tdi, tck, and tms pins. an internal pull-down is provided on the trst pin. power supply bypassing external bypassing is required for each power supply pin. a 0.1 f capacitor must be connected between each v dd and v ss , between v ddd and v ssd , and between v dda and v ssa . the v ss , v ssd , and v ssa planes should be separated, joining at a single point near the external ground connection. the need to reduce high-frequency cou- pling into the analog supply (v dda ) and quiet digital supply (v ddd ) may require inductive beads to be inserted between these lines and the 3.3 v power plane. capacitors used for power supply bypassing should be placed as close as possible to the device pins. parameter symbol test conditions min max unit input leaka g e current all inputs except pulled- up and pulled-down pins pulled-up pins pulled-down pins i l i lpu i lpd 10 80 185 a a a output volta g e: low hi g h v ol v oh i ol = C 5.0 ma* i oh = 5.0 ma ? 0 v dd C 1.0 0.5 v dd v v input capacitance c i 3.0pf load capacitance: all outputs except d [ 7:0 ] d [ 7:0 ] c l c l 50 100 pf pf lucent technologies inc. 187 preliminary data sheet october 2000 TFRA08C13 octal t1/e1 framer lucent technologies inc. outline diagram 352-pin pbga dimensions are in millimeters. 5-4407(f).ar.4 0.56 0.06 1.17 0.05 2.33 0.21 seating plane solder ball 0.60 0.10 0.20 pwb mold compound 35.00 +0.70 C0.00 30.00 a1 ball identifier zone af ae ad ac ab aa y w v u t r g 25 spaces @ 1.27 = 31.75 p n m l k j h 1234567891012141618 222426 20 11 13 15 17 21 19 23 25 f e d c b a 25 spaces a1 ball 0.75 0.15 35.00 0.20 30.00 +0.70 C0.00 0.20 @ 1.27 = 31.75 corner preliminary data sheet TFRA08C13 octal t1/e1 framer october 2000 lucent technologies inc. reserves the right to make changes to the product(s) or information contained herein without notice. n o liability is assumed as a result of their use or application. no rights under any patent accompany the sale of any such product(s) or information. orca is a registered trademark of lucent technologies inc. foundry is a trademark of xilinx, inc. october 2000 ds00-190pdh (replaces ds99-039t1e1) internet: http://www.lucent.com/micro , or for fpga information, http://www.lucent.com/orca e-mail: docmaster@micro.lucent.com n. america: microelectronics group, lucent technologies inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18109-3286 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia pacific: microelectronics group, lucent technologies singapore pte. ltd., 77 science park drive, #03-18 cintech iii, singap ore 118256 tel. (65) 778 8833 , fax (65) 777 7495 china: microelectronics group, lucent technologies (china) co., ltd., a-f2, 23/f, zao fong universe building, 1800 zhong shan xi road, shanghai 200233 p. r. china tel. (86) 21 6440 0468 , ext. 325 , fax (86) 21 6440 0652 japan: microelectronics group, lucent technologies japan ltd., 7-18, higashi-gotanda 2-chome, shinagawa-ku, tokyo 141, japan tel. (81) 3 5421 1600 , fax (81) 3 5421 1700 europe: data requests: microelectronics group dataline: tel. (44) 7000 582 368 , fax (44) 1189 328 148 technical inquiries: germany: (49) 89 95086 0 (munich), united kingdom: (44) 1344 865 900 (ascot), france: (33) 1 40 83 68 00 (paris), sweden: (46) 8 594 607 00 (stockholm), finland: (358) 9 3507670 (helsinki), italy: (39) 02 6608131 (milan), spain: (34) 1 807 1441 (madrid) ordering information device code package temperature comcode (ordering number) TFRA08C13 - db 352-pin pbga C40 c to +85 c 108269754 |
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